355d5584de
According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This is the first commit regarding the optional mask agnostic behavior. Follow-up commits will add this optional behavior for all rvv instructions. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| .. | ||
| trans_privileged.c.inc | ||
| trans_rva.c.inc | ||
| trans_rvb.c.inc | ||
| trans_rvd.c.inc | ||
| trans_rvf.c.inc | ||
| trans_rvh.c.inc | ||
| trans_rvi.c.inc | ||
| trans_rvk.c.inc | ||
| trans_rvm.c.inc | ||
| trans_rvv.c.inc | ||
| trans_rvzfh.c.inc | ||
| trans_svinval.c.inc | ||
| trans_xventanacondops.c.inc | ||