Anton Blanchard c128d39ede target/riscv: Fix vcompress with rvv_ta_all_1s ... vcompress packs vl or less fields into vd, so the tail starts after the last packed field. This could be more clearly expressed in the ISA, but for now this thread helps to explain it: https://github.com/riscv/riscv-v-spec/issues/796 Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241030043538.939712-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-10-31 13:51:24 +10:00
..
insn_trans	target/riscv: implement zicfiss instructions	2024-10-30 11:22:08 +10:00
kvm	target/riscv/kvm: clarify how 'riscv-aia' default works	2024-10-31 13:51:24 +10:00
tcg	target/riscv: AMO operations always raise store/AMO fault	2024-10-30 11:22:08 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: implement zicfiss instructions	2024-10-30 11:22:08 +10:00
cpu_cfg.h	target/riscv: Add zicfiss extension	2024-10-30 11:22:08 +10:00
cpu_helper.c	target/riscv: AMO operations always raise store/AMO fault	2024-10-30 11:22:08 +10:00
cpu_user.h	target/riscv: zicfilp lpad impl and branch tracking	2024-10-30 11:22:08 +10:00
cpu_vendorid.h
cpu-param.h	license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later	2024-09-20 10:11:59 +03:00
cpu-qom.h	target/riscv: Add max32 CPU for RV64 QEMU	2024-10-30 11:22:07 +10:00
cpu.c	target/riscv: Expose zicfiss extension as a cpu property	2024-10-31 13:51:24 +10:00
cpu.h	target/riscv: AMO operations always raise store/AMO fault	2024-10-30 11:22:08 +10:00
crypto_helper.c
csr.c	target/riscv: introduce ssp and enabling controls for zicfiss	2024-10-30 11:22:08 +10:00
debug.c	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
debug.h	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()	2024-06-03 11:12:12 +10:00
helper.h	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	2024-10-30 11:22:08 +10:00
insn32.decode	target/riscv: implement zicfiss instructions	2024-10-30 11:22:08 +10:00
instmap.h
internals.h	target/riscv: mmu changes for zicfiss shadow stack protection	2024-10-30 11:22:08 +10:00
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	2024-10-02 15:11:51 +10:00
m128_helper.c
machine.c	target/riscv: introduce ssp and enabling controls for zicfiss	2024-10-30 11:22:08 +10:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
op_helper.c	target/riscv: save and restore elp state on priv transitions	2024-10-30 11:22:08 +10:00
pmp.c	target/riscv: Introduce elp state and enabling controls for zicfilp	2024-10-30 11:22:08 +10:00
pmp.h	target/riscv: Introduce elp state and enabling controls for zicfilp	2024-10-30 11:22:08 +10:00
pmu.c	target/riscv: Add asserts for out-of-bound access	2024-08-06 14:20:16 +10:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c	target/riscv: Stop timer with infinite timecmp	2024-10-02 15:11:51 +10:00
time_helper.h
trace-events
trace.h
translate.c	target/riscv: implement zicfiss instructions	2024-10-30 11:22:08 +10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	target/riscv: Fix vcompress with rvv_ta_all_1s	2024-10-31 13:51:24 +10:00
vector_internals.c	target/riscv: Fix the element agnostic function problem	2024-06-03 11:12:12 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c