Richard Henderson 119065574d hw/core: Constify TCGCPUOps ... We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>		2021-05-26 15:33:59 -07:00
..
insn_trans	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
arch_dump.c
cpu_bits.h	target/riscv: Remove the unused HSTATUS_WPRI macro	2021-05-11 20:02:07 +10:00
cpu_helper.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
cpu_user.h
cpu-param.h
cpu.c	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
cpu.h	target/riscv: Remove the hardcoded RVXLEN macro	2021-05-11 20:02:07 +10:00
csr.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c
helper.h	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: Fix the RV64H decode comment	2021-05-11 20:02:07 +10:00
instmap.h
internals.h
machine.c
meson.build	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c
pmp.c
pmp.h
trace-events
trace.h
translate.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00