30efbf330a
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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.. | ||
Kconfig | ||
Makefile.objs | ||
riscv_hart.c | ||
riscv_htif.c | ||
sifive_clint.c | ||
sifive_e.c | ||
sifive_gpio.c | ||
sifive_plic.c | ||
sifive_prci.c | ||
sifive_test.c | ||
sifive_u.c | ||
sifive_uart.c | ||
spike.c | ||
trace-events | ||
virt.c |