qemu/hw at 2dda43bacc79f8e283702614745cd700c637de64 - qemu

History

Peter Maydell 2dda43bacc target-arm queue:

* more A64 Neon instructions
  * fixes to reset CBAR values for A9 and A15 boards
  * fix accesses to PMCR register in -icount mode
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABCAAGBQJTJ3GEAAoJEDwlJe0UNgzevGcP/2ftt3PRACZ9BqUh6s1xBW0/
 /dqcEIildxZYxmTHDH+g5t2ueho+o+qhpmXf+lHO0C+nl86SRm/DVJj+tmuUoWdf
 5BA1eOVjQnvrnmQx72/CS4NI4t0npoYf7Cserkpm9ZOdzweJy68YHZZRVpHLfldS
 Ba7W749EsGPnd5ZEhnplwGSIjM3ZUfixm3yJSsGnHAf6KEskkVKjUUI2lZWecT81
 5f14qN6F7qk7XvH9HGOWZktiKGfaSLVXzZGsmdq6oDVTr+2ZMkoFxn7jMFm4EHtW
 cTDVcwN9Y6tFM2Pm7PIxzXmP9lTc5L+ghVXn9XhuY9OS7ZFD46r/sh3Lkhypq+WP
 SfJaPOG5zZuKkmj+hyO+08hjLxR+TJDIKr26tY62yGrteWN+SkzoJuO6Gn17uuC8
 UhAqjbLuunhSlJA7oy42i7YcR84LXemMCplbqBY/v7W54ZWrxV+QgNKiLtbsIpWF
 tGg8R85jkjE7lV7dfaeK7N+vQjGIMwzT+g9sYyS3zsY0ubFnkIMa04Zn4gMsCheU
 azmyCfQOCmdN71CEEN6rbTWL3AtWw2Oss1RxK1iQu5J8+YgC2TvNsb4hE4K5KctX
 utvoPoVScBWZvvX2zvMv43+qz74arSTOxuBCMW9Gf0pEQA1cT0GdYzRrb3g+8CCp
 n3GuAoTMj2d72c2WO36I
 =YFAg
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140317' into staging

target-arm queue:
 * more A64 Neon instructions
 * fixes to reset CBAR values for A9 and A15 boards
 * fix accesses to PMCR register in -icount mode

# gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits)
  scripts/qemu-binfmt-conf.sh: Add AArch64 registration
  target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
  target-arm: A64: Implement FCVTXN
  target-arm: A64: Implement scalar saturating narrow ops
  target-arm: A64: Move handle_2misc_narrow function
  target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
  softfloat: export squash_input_denormal functions
  target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
  target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
  exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
  target-arm: A64: Implement FRINT*
  target-arm: A64: Implement SRI
  target-arm: A64: Add FRECPX (reciprocal exponent)
  target-arm: A64: List unsupported shift-imm opcodes
  target-arm: A64: Implement FCVTL
  target-arm: A64: Implement FCVTN
  target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
  target-arm: A64: Implement SHLL, SHLL2
  target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
  target-arm: A64: Saturating and narrowing shift ops
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2014-03-18 14:31:42 +00:00

9pfs

hw/9pfs: use g_strdup_printf() instead of PATH_MAX limitation

2014-03-04 00:57:57 +05:30

acpi

QOM infrastructure fixes and device conversions

2014-02-20 13:05:48 +00:00

alpha

exec: Make stq_*_phys input an AddressSpace

2014-02-11 22:57:12 +10:00

arm

virt: Set reset-cbar on CPUs