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Philippe Mathieu-Daudé 66125f9360 target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' 
CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-6-philmd@linaro.org>
2023-11-07 12:13:27 +01:00
..
insn_trans
target/riscv: Replace Zvbb checking by Zvkb
2023-11-07 11:06:02 +10:00
kvm
target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot
2023-11-07 11:06:02 +10:00
tcg
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
arch_dump.c
…
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
2023-11-07 11:02:17 +10:00
cpu_cfg.h
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
cpu_helper.c
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
2023-11-07 11:02:17 +10:00
cpu_user.h
…
cpu_vendorid.h
…
cpu-param.h
…
cpu-qom.h
target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
2023-11-07 12:13:27 +01:00
cpu.c
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
cpu.h
target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
2023-11-07 12:13:27 +01:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: Don't assume PMU counters are continuous
2023-11-07 11:06:02 +10:00
debug.c
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
debug.h
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
fpu_helper.c
riscv: Add support for the Zfa extension
2023-07-10 22:29:20 +10:00
gdbstub.c
target/riscv: rename ext_icsr to ext_zicsr
2023-11-07 11:02:17 +10:00
helper.h
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
insn16.decode
…
insn32.decode
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
instmap.h
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
2022-09-07 09:18:32 +02:00
internals.h
…
Kconfig
…
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
meson.build
target/riscv: move KVM only files to kvm subdir
2023-10-12 12:20:24 +10:00
monitor.c
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
op_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
pmp.c
target/riscv: pmp: Ignore writes when RW=01
2023-11-07 11:06:02 +10:00
pmp.h
target/riscv: pmp: Clear pmp/smepmp bits on reset
2023-11-07 11:06:02 +10:00
pmu.c
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
pmu.h
target/riscv: Use existing PMU counter mask in FDT generation
2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c
target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h
…
time_helper.c
…
time_helper.h
…
trace-events
…
trace.h
…
translate.c
accel/tcg: Replace CPUState.env_ptr with cpu_env()
2023-10-04 11:03:54 -07:00
vcrypto_helper.c
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
vector_helper.c
target/riscv: Fix vfwmaccbf16.vf
2023-10-12 12:50:13 +10:00
vector_internals.c
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:54 +10:00
vector_internals.h
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:55 +10:00
xthead.decode
…
XVentanaCondOps.decode
…
zce_helper.c
…