Frank Chang 2d258b428b target/riscv: zfh: implement zfhmin extension ...

Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.

If enabled, only the following instructions from Zfh extension are
included:
  * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
  * If D extension is present: fcvt.d.h, fcvt.h.d

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-12-20 14:51:36 +10:00

..

insn_trans

target/riscv: zfh: implement zfhmin extension

2021-12-20 14:51:36 +10:00

arch_dump.c

…

bitmanip_helper.c

target/riscv: Add rev8 instruction, removing grev/grevi

2021-10-07 08:41:33 +10:00

cpu_bits.h

target/riscv: remove force HS exception

2021-10-29 16:54:45 +10:00

cpu_helper.c

target/riscv: Make riscv_cpu_tlb_fill sysemu only

2021-11-02 07:00:52 -04:00

cpu_user.h

…

cpu-param.h

…

cpu.c

target/riscv: zfh: add Zfh cpu property

2021-12-20 14:51:36 +10:00

cpu.h

target/riscv: zfh: implement zfhmin extension

2021-12-20 14:51:36 +10:00

csr.c

target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

2021-10-28 14:39:23 +10:00

fpu_helper.c

target/riscv: zfh: half-precision floating-point classify

2021-12-20 14:51:36 +10:00

gdbstub.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

helper.h

target/riscv: zfh: half-precision floating-point classify

2021-12-20 14:51:36 +10:00

insn16.decode

…

insn32.decode

target/riscv: zfh: half-precision floating-point classify

2021-12-20 14:51:36 +10:00

instmap.h

…

internals.h

target/riscv: zfh: half-precision computational

2021-12-20 14:51:36 +10:00

Kconfig

meson: Introduce target-specific Kconfig

2021-07-09 18:21:34 +02:00

machine.c

target/riscv: machine: Sort the .subsections

2021-11-17 19:18:22 +10:00

meson.build

…

monitor.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

op_helper.c

target/riscv: Reorg csr instructions

2021-09-01 11:59:12 +10:00

pmp.c

target/riscv: pmp: Fix some typos

2021-07-15 08:56:00 +10:00

pmp.h

…

trace-events

…

trace.h

…

translate.c

target/riscv: zfh: implement zfhmin extension

2021-12-20 14:51:36 +10:00

vector_helper.c

…