qemu/target
Peter Maydell 2d12bb96bd target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate()
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
of those will pass 'secure == true' in the callsites in ptw.c.

As it happens in all of our callsites in ptw.c we either avoid making
the call or else avoid using the returned value if we're doing a
translation for Root, so this is not a behaviour change even if the
experimental FEAT_RME is enabled.  But it is less confusing in the
ptw.c code if we avoid the use of a bool secure that duplicates some
of the information in the ArmSecuritySpace argument.

Make arm_hcr_el2_eff_secstate() take an ARMSecuritySpace argument
instead. Because we always want to know the HCR_EL2 for the
security state defined by the current effective value of
SCR_EL3.{NSE,NS}, it makes no sense to pass ARMSS_Root here,
and we assert that callers don't do that.

To avoid the assert(), we thus push the call to
arm_hcr_el2_eff_secstate() down into the cases in
regime_translation_disabled() that need it, rather than calling the
function and ignoring the result for the Root space translations.
All other calls to this function in ptw.c are already in places
where we have confirmed that the mmu_idx is a stage 2 translation
or that the regime EL is not 3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-7-peter.maydell@linaro.org
2023-08-22 17:31:07 +01:00
..
alpha other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
arm target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() 2023-08-22 17:31:07 +01:00
avr target/avr: Fix handling of interrupts above 33. 2023-07-08 07:24:38 +03:00
cris other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
hexagon target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
hppa target/hppa: Move iaoq registers and thus reduce generated code size 2023-08-04 00:02:56 +02:00
i386 kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
loongarch other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
m68k target/m68k: Fix semihost lseek offset computation 2023-08-01 23:52:23 +02:00
microblaze other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
mips mips: Report an error when KVM_VM_MIPS_VZ is unavailable 2023-08-22 17:31:03 +01:00
nios2 target/nios2: Fix semihost lseek offset computation 2023-08-01 23:52:23 +02:00
openrisc target/openrisc: Set EPCR to next PC on FPE exceptions 2023-07-31 22:01:03 +01:00
ppc kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
riscv kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
rx other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
s390x kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
sh4 target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
sparc trivial-patches 25-07-2023 2023-07-25 16:30:52 +01:00
tricore target/tricore: Rename tricore_feature 2023-07-25 17:18:51 +03:00
xtensa target/xtensa: Assert that interrupt level is within bounds 2023-07-06 13:26:43 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00