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trivial-patches 25-07-2023

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial-patches 25-07-2023

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# gpg: Signature made Tue 25 Jul 2023 15:23:52 BST
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
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* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu:
  qapi: Correct "eg." to "e.g." in documentation
  hw/pci: add comment to explain checking for available function 0 in pci hotplug
  target/tricore: Rename tricore_feature
  hw/9pfs: spelling fixes
  other architectures: spelling fixes
  arm: spelling fixes
  s390x: spelling fixes
  migration: spelling fixes

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-07-25 16:30:51 +01:00
commit 0b58dc4561
78 changed files with 125 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
host/include/aarch64/host/cpuinfo.h
View File

@ -1,6 +1,6 @@
/*
* SPDX-License-Identifier: GPL-2.0-or-later
* Host specific cpu indentification for AArch64.
* Host specific cpu identification for AArch64.
*/
#ifndef HOST_CPUINFO_H

2
host/include/generic/host/cpuinfo.h
View File

@ -1,4 +1,4 @@
/*
* No host specific cpu indentification.
* No host specific cpu identification.
* SPDX-License-Identifier: GPL-2.0-or-later
*/

8
hw/9pfs/9p-local.c
View File

@ -624,7 +624,7 @@ static ssize_t local_pwritev(FsContext *ctx, V9fsFidOpenState *fs,
/*
* Initiate a writeback. This is not a data integrity sync.
* We want to ensure that we don't leave dirty pages in the cache
* after write when writeout=immediate is sepcified.
* after write when writeout=immediate is specified.
*/
sync_file_range(fs->fd, offset, ret,
SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRITE);
@ -843,7 +843,7 @@ static int local_open2(FsContext *fs_ctx, V9fsPath *dir_path, const char *name,
}
credp->fc_mode = credp->fc_mode | S_IFREG;
if (fs_ctx->export_flags & V9FS_SM_MAPPED) {
/* Set cleint credentials in xattr */
/* Set client credentials in xattr */
err = local_set_xattrat(dirfd, name, credp);
} else {
err = local_set_mapped_file_attrat(dirfd, name, credp);
@ -912,7 +912,7 @@ static int local_symlink(FsContext *fs_ctx, const char *oldpath,
if (write_size != oldpath_size) {
goto err_end;
}
/* Set cleint credentials in symlink's xattr */
/* Set client credentials in symlink's xattr */
credp->fc_mode = credp->fc_mode | S_IFLNK;
if (fs_ctx->export_flags & V9FS_SM_MAPPED) {
@ -1418,7 +1418,7 @@ static int local_ioc_getversion_init(FsContext *ctx, LocalData *data, Error **er
struct statfs stbuf;
/*
* use ioc_getversion only if the ioctl is definied
* use ioc_getversion only if the ioctl is defined
*/
if (fstatfs(data->mountfd, &stbuf) < 0) {
error_setg_errno(errp, errno,

2
hw/9pfs/9p-proxy.c
View File

@ -767,7 +767,7 @@ static ssize_t proxy_pwritev(FsContext *ctx, V9fsFidOpenState *fs,
/*
* Initiate a writeback. This is not a data integrity sync.
* We want to ensure that we don't leave dirty pages in the cache
* after write when writeout=immediate is sepcified.
* after write when writeout=immediate is specified.
*/
sync_file_range(fs->fd, offset, ret,
SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRITE);

2
hw/9pfs/9p-synth.c
View File

@ -493,7 +493,7 @@ static int synth_name_to_path(FsContext *ctx, V9fsPath *dir_path,
node = dir_node;
goto out;
}
/* search for the name in the childern */
/* search for the name in the children */
rcu_read_lock();
QLIST_FOREACH(node, &dir_node->child, sibling) {
if (!strcmp(node->name, name)) {

2
hw/9pfs/9p-util.h
View File

@ -48,7 +48,7 @@ static inline uint64_t makedev_dotl(uint32_t dev_major, uint32_t dev_minor)
/*
* Converts given device number from host's device number format to Linux
* device number format. As both the size of type dev_t and encoding of
* dev_t is system dependant, we have to convert them for Linux guests if
* dev_t is system dependent, we have to convert them for Linux guests if
* host is not running Linux.
*/
static inline uint64_t host_dev_to_dotl_dev(dev_t dev)

4
hw/9pfs/9p.c
View File

@ -644,7 +644,7 @@ static inline uint64_t mirror64bit(uint64_t value)
}
/*
* Parameter k for the Exponential Golomb algorihm to be used.
* Parameter k for the Exponential Golomb algorithm to be used.
*
* The smaller this value, the smaller the minimum bit count for the Exp.
* Golomb generated affixes will be (at lowest index) however for the
@ -1039,7 +1039,7 @@ static void coroutine_fn pdu_complete(V9fsPDU *pdu, ssize_t len)
* Sending a reply would confuse clients because they would
* assume that any EINTR is the actual result of the operation,
* rather than a consequence of the cancellation. However, if
* the operation completed (succesfully or with an error other
* the operation completed (successfully or with an error other
* than caused be cancellation), we do send out that reply, both
* for efficiency and to avoid confusing the rest of the state machine
* that assumes passing a non-error here will mean a successful

2
hw/9pfs/9p.h
View File

@ -304,7 +304,7 @@ typedef struct VariLenAffix {
AffixType_t type; /* Whether this affix is a suffix or a prefix. */
uint64_t value; /* Actual numerical value of this affix. */
/*
* Lenght of the affix, that is how many (of the lowest) bits of ``value``
* Length of the affix, that is how many (of the lowest) bits of ``value``
* must be used for appending/prepending this affix to its final resulting,
* unique number.
*/

2
hw/arm/aspeed.c
View File

@ -1565,7 +1565,7 @@ static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
/* U10 24C08 connects to SDA/SCL Groupt 1 by default */
/* U10 24C08 connects to SDA/SCL Group 1 by default */
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);

2
hw/arm/mps2-tz.c
View File

@ -1205,7 +1205,7 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
{
/*
* The MPS2 TZ FPGA images have IDAUs in them which are connected to
* the Master Security Controllers. Thes have the same logic as
* the Master Security Controllers. These have the same logic as
* is used by the IoTKit for the IDAU connected to the CPU, except
* that MSCs don't care about the NSC attribute.
*/

4
hw/intc/arm_gic.c
View File

@ -239,7 +239,7 @@ static inline bool gic_lr_entry_is_free(uint32_t entry)
}
/* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
* corrsponding bit in EISR is set.
* corresponding bit in EISR is set.
*/
static inline bool gic_lr_entry_is_eoi(uint32_t entry)
{
@ -1333,7 +1333,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
/* ??? This currently clears the pending bit for all CPUs, even
for per-CPU interrupts. It's unclear whether this is the
corect behavior. */
correct behavior. */
if (value & (1 << i)) {
GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
}

2
hw/intc/arm_gicv3_redist.c
View File

@ -494,7 +494,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
/* Only the ProcessorSleep bit is writable. When the guest sets
* it, it requests that we transition the channel between the
* redistributor and the cpu interface to quiescent, and that
* we set the ChildrenAsleep bit once the inteface has reached the
* we set the ChildrenAsleep bit once the interface has reached the
* quiescent state.
* Setting the ProcessorSleep to 0 reverses the quiescing, and
* ChildrenAsleep is cleared once the transition is complete.

2
hw/intc/armv7m_nvic.c
View File

@ -894,7 +894,7 @@ int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
vec->active = 0;
if (vec->level) {
/* Re-pend the exception if it's still held high; only
* happens for extenal IRQs
* happens for external IRQs
*/
assert(irq >= NVIC_FIRST_IRQ);
vec->pending = 1;

2
hw/intc/s390_flic_kvm.c
View File

@ -380,7 +380,7 @@ static void kvm_s390_release_adapter_routes(S390FLICState *fs,
* @size: ignored
*
* Note: Pass buf and len to kernel. Start with one page and
* increase until buffer is sufficient or maxium size is
* increase until buffer is sufficient or maximum size is
* reached
*/
static int kvm_flic_save(QEMUFile *f, void *opaque, size_t size,

2
hw/m68k/next-cube.c
View File

@ -734,7 +734,7 @@ static void next_irq(void *opaque, int number, int level)
M68kCPU *cpu = s->cpu;
int shift = 0;
/* first switch sets interupt status */
/* first switch sets interrupt status */
/* DPRINTF("IRQ %i\n",number); */
switch (number) {
/* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */

2
hw/m68k/next-kbd.c
View File

@ -37,7 +37,7 @@
OBJECT_DECLARE_SIMPLE_TYPE(NextKBDState, NEXTKBD)
/* following defintions from next68k netbsd */
/* following definitions from next68k netbsd */
#define CSR_INT 0x00800000
#define CSR_DATA 0x00400000

2
hw/m68k/virt.c
View File

@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* QEMU Vitual M68K Machine
* QEMU Virtual M68K Machine
*
* (c) 2020 Laurent Vivier <laurent@vivier.eu>
*

2
hw/microblaze/petalogix_ml605_mmu.c
View File

@ -104,7 +104,7 @@ petalogix_ml605_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
* 10th parameter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0);

2
hw/misc/allwinner-r40-dramc.c
View File

@ -368,7 +368,7 @@ static const MemoryRegionOps allwinner_r40_detect_ops = {
/*
* mctl_r40_detect_rank_count in u-boot will write the high 1G of DDR
* to detect wether the board support dual_rank or not. Create a virtual memory
* to detect whether the board support dual_rank or not. Create a virtual memory
* if the board's ram_size less or equal than 1G, and set read time out flag of
* REG_DRAMCTL_PGSR when the user touch this high dram.
*/

2
hw/misc/exynos4210_rng.c
View File

@ -1,5 +1,5 @@
/*
* Exynos4210 Pseudo Random Nubmer Generator Emulation
* Exynos4210 Pseudo Random Number Generator Emulation
*
* Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
*

11
hw/pci/pci.c
View File

@ -1183,9 +1183,14 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
PCI_SLOT(devfn), PCI_FUNC(devfn), name,
bus->devices[devfn]->name, bus->devices[devfn]->qdev.id);
return NULL;
} else if (dev->hotplugged &&
!pci_is_vf(pci_dev) &&
pci_get_function_0(pci_dev)) {
} /*
* Populating function 0 triggers a scan from the guest that
* exposes other non-zero functions. Hence we need to ensure that
* function 0 wasn't added yet.
*/
else if (dev->hotplugged &&
!pci_is_vf(pci_dev) &&
pci_get_function_0(pci_dev)) {
error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
" new func %s cannot be exposed to guest.",
PCI_SLOT(pci_get_function_0(pci_dev)->devfn),

8
hw/sparc/sun4m_iommu.c
View File

@ -96,10 +96,10 @@
#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK 0x801f000f
#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */

2
include/hw/arm/fsl-imx7.h
View File

@ -165,7 +165,7 @@ enum FslIMX7MemoryMap {
* Some versions of the reference manual claim that UART2 is @
* 0x30870000, but experiments with HW + DT files in upstream
* Linux kernel show that not to be true and that block is
* acutally located @ 0x30890000
* actually located @ 0x30890000
*/
FSL_IMX7_UART2_ADDR = 0x30890000,
FSL_IMX7_UART3_ADDR = 0x30880000,

2
include/hw/intc/armv7m_nvic.h
View File

@ -74,7 +74,7 @@ struct NVICState {
*/
bool vectpending_is_s_banked;
int exception_prio; /* group prio of the highest prio active exception */
int vectpending_prio; /* group prio of the exeception in vectpending */
int vectpending_prio; /* group prio of the exception in vectpending */
MemoryRegion sysregmem;

2
include/hw/s390x/s390-pci-bus.h
View File

@ -184,7 +184,7 @@ enum ZpciIoatDtype {
* The following states make up the "configured" meta-state:
* disabled: device is configured but not enabled; transition between this
* state and enabled via clp enable/disable
* enbaled: device is ready for use; transition to disabled via clp disable;
* enabled: device is ready for use; transition to disabled via clp disable;
* may enter an error state
* blocked: ignore all DMA and interrupts; transition back to enabled or from
* error state via mpcifc

2
include/hw/s390x/sclp.h
View File

@ -87,7 +87,7 @@
* - we work on a private copy of the SCCB, since there are several length
* fields, that would cause a security nightmare if we allow the guest to
* alter the structure while we parse it. We cannot use ldl_p and friends
* either without doing pointer arithmetics
* either without doing pointer arithmetic
* So we have to double check that all users of sclp data structures use the
* right endianness wrappers.
*/

2
migration/migration-stats.c
View File

@ -48,7 +48,7 @@ uint64_t migration_rate_get(void)
void migration_rate_set(uint64_t limit)
{
/*
* 'limit' is per second. But we check it each BUFER_DELAY miliseconds.
* 'limit' is per second. But we check it each BUFFER_DELAY milliseconds.
*/
stat64_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO);
}

4
migration/migration.h
View File

@ -134,7 +134,7 @@ struct MigrationIncomingState {
/*
* Always set by the main vm load thread only, but can be read by the
* postcopy preempt thread. "volatile" makes sure all reads will be
* uptodate across cores.
* up-to-date across cores.
*/
volatile PreemptThreadStatus preempt_thread_status;
/*
@ -409,7 +409,7 @@ struct MigrationState {
* channel itself.
*
* - postcopy preempt channel will be created at the switching phase
* from precopy -> postcopy (to avoid race condtion of misordered
* from precopy -> postcopy (to avoid race condition of misordered
* creation of channels).
*
* NOTE: See message-id <ZBoShWArKDPpX/D7@work-vm> on qemu-devel

2
migration/multifd-zlib.c
View File

@ -57,7 +57,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp)
err_msg = "deflate init failed";
goto err_free_z;
}
/* This is the maxium size of the compressed buffer */
/* This is the maximum size of the compressed buffer */
z->zbuff_len = compressBound(MULTIFD_PACKET_SIZE);
z->zbuff = g_try_malloc(z->zbuff_len);
if (!z->zbuff) {

2
migration/multifd-zstd.c
View File

@ -68,7 +68,7 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **errp)
p->id, ZSTD_getErrorName(res));
return -1;
}
/* This is the maxium size of the compressed buffer */
/* This is the maximum size of the compressed buffer */
z->zbuff_len = ZSTD_compressBound(MULTIFD_PACKET_SIZE);
z->zbuff = g_try_malloc(z->zbuff_len);
if (!z->zbuff) {

2
migration/multifd.c
View File

@ -878,7 +878,7 @@ static void multifd_new_send_channel_cleanup(MultiFDSendParams *p,
qemu_sem_post(&p->sem_sync);
/*
* Although multifd_send_thread is not created, but main migration
* thread neet to judge whether it is running, so we need to mark
* thread need to judge whether it is running, so we need to mark
* its status.
*/
p->quit = true;

2
migration/savevm.c
View File

@ -117,7 +117,7 @@ static struct mig_cmd_args {
* The format of arguments is depending on postcopy mode:
* - postcopy RAM only
* uint64_t host page size
* uint64_t taget page size
* uint64_t target page size
*
* - postcopy RAM and postcopy dirty bitmaps
* format is the same as for postcopy RAM only

2
migration/trace-events
View File

@ -184,7 +184,7 @@ source_return_path_thread_shut(uint32_t val) "0x%x"
source_return_path_thread_resume_ack(uint32_t v) "%"PRIu32
source_return_path_thread_switchover_acked(void) ""
migration_thread_low_pending(uint64_t pending) "%" PRIu64
migrate_transferred(uint64_t tranferred, uint64_t time_spent, uint64_t bandwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " bandwidth %" PRIu64 " max_size %" PRId64
migrate_transferred(uint64_t transferred, uint64_t time_spent, uint64_t bandwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " bandwidth %" PRIu64 " max_size %" PRId64
process_incoming_migration_co_end(int ret, int ps) "ret=%d postcopy-state=%d"
process_incoming_migration_co_postcopy_end_main(void) ""
postcopy_preempt_enabled(bool value) "%d"

2
qapi/char.json
View File

@ -18,7 +18,7 @@
# @filename: the filename of the character device
#
# @frontend-open: shows whether the frontend device attached to this
# backend (eg. with the chardev=... option) is in open or closed
# backend (e.g. with the chardev=... option) is in open or closed
# state (since 2.1)
#
# Notes: @filename is encoded using the QEMU command line character

2
qapi/misc.json
View File

@ -18,7 +18,7 @@
# fail and the FD will be closed.
#
# @protocol: protocol name. Valid names are "vnc", "spice",
# "@dbus-display" or the name of a character device (eg. from
# "@dbus-display" or the name of a character device (e.g. from
# -chardev id=XXXX)
#
# @fdname: file descriptor name previously passed via 'getfd' command

4
target/alpha/cpu.h
View File

@ -191,7 +191,7 @@ enum {
That said, we're only emulating Unix PALcode, and not attempting VMS,
so we don't need to implement Executive and Supervisor. QEMU's own
PALcode cheats and usees the KSEG mapping for its code+data rather than
PALcode cheats and uses the KSEG mapping for its code+data rather than
physical addresses. */
#define MMU_KERNEL_IDX 0
@ -362,7 +362,7 @@ enum {
The Unix PALcode only uses bit 4. */
#define PS_USER_MODE 8u
/* CPUAlphaState->flags constants. These are layed out so that we
/* CPUAlphaState->flags constants. These are laid out so that we
can set or reset the pieces individually by assigning to the byte,
or manipulated as a whole. */

2
target/alpha/translate.c
View File

@ -2893,7 +2893,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
the first fp insn of the TB. Alternately we could define a proper
default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
to reset the FP_STATUS to that default at the end of any TB that
changes the default. We could even (gasp) dynamiclly figure out
changes the default. We could even (gasp) dynamically figure out
what default would be most efficient given the running program. */
ctx->tb_rm = -1;
/* Similarly for flush-to-zero. */

2
target/arm/cpu.c
View File

@ -677,7 +677,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
}
/*
* The PSTATE bits only mask the interrupt if we have not overriden the
* The PSTATE bits only mask the interrupt if we have not overridden the
* ability above.
*/
return unmasked || pstate_unmasked;

2
target/arm/cpu.h
View File

@ -2592,7 +2592,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
return aa64;
}
/* Function for determing whether guest cp register reads and writes should
/* Function for determining whether guest cp register reads and writes should
* access the secure or non-secure bank of a cp register. When EL3 is
* operating in AArch32 state, the NS-bit determines whether the secure
* instance of a cp register should be used. When EL3 is AArch64 (or if

2
target/arm/cpu64.c
View File

@ -95,7 +95,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
if (kvm_enabled()) {
/*
* For KVM we have to automatically enable all supported unitialized
* For KVM we have to automatically enable all supported uninitialized
* lengths, even when the smaller lengths are not all powers-of-two.
*/
vq_map |= vq_supported & ~vq_init & vq_mask;

4
target/arm/helper.c
View File

@ -1674,7 +1674,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
* pmevtyper_rawwrite is called between a pair of pmu_op_start and
* pmu_op_finish calls when loading saved state for a migration. Because
* we're potentially updating the type of event here, the value written to
* c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
* c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
* different counter type. Therefore, we need to set this value to the
* current count for the counter type we're writing so that pmu_op_finish
* has the correct count for its calculation.
@ -7009,7 +7009,7 @@ static const ARMCPRegInfo rme_reginfo[] = {
/*
* QEMU does not have a way to invalidate by physical address, thus
* invalidating a range of physical addresses is accomplished by
* flushing all tlb entries in the outer sharable domain,
* flushing all tlb entries in the outer shareable domain,
* just like PAALLOS.
*/
{ .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,

2
target/arm/tcg/m_helper.c
View File

@ -148,7 +148,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
* R: 0 because unpriv and A flag not set
* SRVALID: 0 because NS
* MRVALID: 0 because unpriv and A flag not set
* SREGION: 0 becaus SRVALID is 0
* SREGION: 0 because SRVALID is 0
* MREGION: 0 because MRVALID is 0
*/
return 0;

4
target/arm/tcg/translate-a64.c
View File

@ -182,7 +182,7 @@ void gen_a64_update_pc(DisasContext *s, target_long diff)
* + for EL2 and EL3 there is only one TBI bit, and if it is set
* then the address is zero-extended, clearing bits [63:56]
* + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
* and TBI1 controls addressses with bit 55 == 1.
* and TBI1 controls addresses with bit 55 == 1.
* If the appropriate TBI bit is set for the address then
* the address is sign-extended from bit 55 into bits [63:56]
*
@ -2313,7 +2313,7 @@ static void handle_sys(DisasContext *s, bool isread,
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/*
* A write to any coprocessor regiser that ends a TB
* A write to any coprocessor register that ends a TB
* must rebuild the hflags for the next TB.
*/
gen_rebuild_hflags(s);

4
target/arm/tcg/translate-mve.c
View File

@ -2182,7 +2182,7 @@ static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
* execution if it is not in an IT block. For us this means
* only that if PSR.ECI says we should not be executing the beat
* corresponding to the lane of the vector register being accessed
* then we should skip perfoming the move, and that we need to do
* then we should skip performing the move, and that we need to do
* the usual check for bad ECI state and advance of ECI state.
* (If PSR.ECI is non-zero then we cannot be in an IT block.)
*/
@ -2225,7 +2225,7 @@ static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
* execution if it is not in an IT block. For us this means
* only that if PSR.ECI says we should not be executing the beat
* corresponding to the lane of the vector register being accessed
* then we should skip perfoming the move, and that we need to do
* then we should skip performing the move, and that we need to do
* the usual check for bad ECI state and advance of ECI state.
* (If PSR.ECI is non-zero then we cannot be in an IT block.)
*/

2
target/arm/tcg/translate-sve.c
View File

@ -1841,7 +1841,7 @@ TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext)
/* Perform an inline saturating addition of a 32-bit value within
* a 64-bit register. The second operand is known to be positive,
* which halves the comparisions we must perform to bound the result.
* which halves the comparisons we must perform to bound the result.
*/
static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{

2
target/arm/tcg/translate-vfp.c
View File

@ -144,7 +144,7 @@ static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)
* Generate code for M-profile FP context handling: update the
* ownership of the FP context, and create a new context if
* necessary. This corresponds to the parts of the pseudocode
* ExecuteFPCheck() after the inital PreserveFPState() call.
* ExecuteFPCheck() after the initial PreserveFPState() call.
*/
static void gen_update_fp_context(DisasContext *s)
{

2
target/arm/tcg/vec_helper.c
View File

@ -2626,7 +2626,7 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
* Process the entire segment at once, writing back the
* results only after we've consumed all of the inputs.
*
* Key to indicies by column:
* Key to indices by column:
* i j i k j k
*/
sum00 = a[s + H4(0 + 0)];

6
target/cris/helper.c
View File

@ -113,7 +113,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PRV10_BRP] = env->pc;
@ -169,7 +169,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PR_ERP] = env->pc;
@ -228,7 +228,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
/* Clear the excption_index to avoid spurios hw_aborts for recursive
/* Clear the excption_index to avoid spurious hw_aborts for recursive
bus faults. */
cs->exception_index = -1;

2
target/cris/op_helper.c
View File

@ -231,7 +231,7 @@ static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
{
unsigned int x, z, mask;
/* Extended arithmetics, leave the z flag alone. */
/* Extended arithmetic, leave the z flag alone. */
x = env->cc_x;
mask = env->cc_mask | X_FLAG;
if (x) {

16
target/cris/translate.c
View File

@ -342,7 +342,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
tcg_gen_add_tl(d, d, t);
}
/* Extended arithmetics on CRIS. */
/* Extended arithmetic on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
TCGv c;
@ -646,7 +646,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
/* Extended arithmetics. */
/* Extended arithmetic. */
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
@ -659,7 +659,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
@ -685,7 +685,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
/* Extended arithmetics. */
/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
@ -708,7 +708,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
default:
@ -2924,12 +2924,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
* On QEMU care needs to be taken when a branch+delayslot sequence is broken
* and the branch and delayslot don't share pages.
*
* The TB contaning the branch insn will set up env->btarget and evaluate
* The TB containing the branch insn will set up env->btarget and evaluate
* env->btaken. When the translation loop exits we will note that the branch
* sequence is broken and let env->dslot be the size of the branch insn (those
* vary in length).
*
* The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
* The TB containing the delayslot will have the PC of its real insn (i.e no lsb
* set). It will also expect to have env->dslot setup with the size of the
* delay slot so that env->pc - env->dslot point to the branch insn. This TB
* will execute the dslot and take the branch, either to btarget or just one
@ -3143,7 +3143,7 @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_UPDATE:
/* Indicate that interupts must be re-evaluated before the next TB. */
/* Indicate that interrupts must be re-evaluated before the next TB. */
tcg_gen_exit_tb(NULL, 0);
break;
default:

4
target/hppa/cpu.h
View File

@ -35,7 +35,7 @@
#define MMU_PHYS_IDX 4
#define TARGET_INSN_START_EXTRA_WORDS 1
/* Hardware exceptions, interupts, faults, and traps. */
/* Hardware exceptions, interrupts, faults, and traps. */
#define EXCP_HPMC 1 /* high priority machine check */
#define EXCP_POWER_FAIL 2
#define EXCP_RC 3 /* recovery counter */
@ -276,7 +276,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
/* TB lookup assumes that PC contains the complete virtual address.
If we leave space+offset separate, we'll get ITLB misses to an
incomplete virtual address. This also means that we must separate
out current cpu priviledge from the low bits of IAOQ_F. */
out current cpu privilege from the low bits of IAOQ_F. */
#ifdef CONFIG_USER_ONLY
*pc = env->iaoq_f & -4;
*cs_base = env->iaoq_b & -4;

2
target/hppa/int_helper.c
View File

@ -37,7 +37,7 @@ static void eval_interrupt(HPPACPU *cpu)
/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus
* can write to this word to raise an external interrupt on the target CPU.
* This includes the system controler (DINO) for regular devices, or
* This includes the system controller (DINO) for regular devices, or
* another CPU for SMP interprocessor interrupts.
*/
static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)

2
target/hppa/translate.c
View File

@ -1964,7 +1964,7 @@ static void do_page_zero(DisasContext *ctx)
{
/* If by some means we get here with PSW[N]=1, that implies that
the B,GATE instruction would be skipped, and we'd fault on the
next insn within the privilaged page. */
next insn within the privileged page. */
switch (ctx->null_cond.c) {
case TCG_COND_NEVER:
break;

2
target/loongarch/cpu-csr.h
View File

@ -10,7 +10,7 @@
#include "hw/registerfields.h"
/* Base on kernal definitions: arch/loongarch/include/asm/loongarch.h */
/* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */
/* Basic CSRs */
#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */

4
target/m68k/helper.c
View File

@ -590,10 +590,10 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
#define DUMP_CACHEFLAGS(a) \
switch (a & M68K_DESC_CACHEMODE) { \
case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \
case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
qemu_printf("T"); \
break; \
case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \
case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
qemu_printf("C"); \
break; \
case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \

2
target/microblaze/cpu.h
View File

@ -205,7 +205,7 @@ typedef struct CPUArchState CPUMBState;
#define PVR10_TARGET_FAMILY_MASK 0xFF000000
#define PVR10_ASIZE_SHIFT 18
/* MMU descrtiption */
/* MMU description */
#define PVR11_USE_MMU 0xC0000000
#define PVR11_MMU_ITLB_SIZE 0x38000000
#define PVR11_MMU_DTLB_SIZE 0x07000000

2
target/openrisc/cpu.h
View File

@ -290,7 +290,7 @@ typedef struct CPUArchState {
int is_counting;
uint32_t picmr; /* Interrupt mask register */
uint32_t picsr; /* Interrupt contrl register*/
uint32_t picsr; /* Interrupt control register */
#endif
} CPUOpenRISCState;

4
target/openrisc/translate.c
View File

@ -273,7 +273,7 @@ static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0);
/* The result of divide-by-zero is undefined.
Supress the host-side exception by dividing by 1. */
Suppress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_ov);
tcg_gen_div_tl(dest, srca, t0);
@ -287,7 +287,7 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0);
/* The result of divide-by-zero is undefined.
Supress the host-side exception by dividing by 1. */
Suppress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_cy);
tcg_gen_divu_tl(dest, srca, t0);

4
target/rx/translate.c
View File

@ -2066,7 +2066,7 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
tcg_gen_movi_i32(cpu_psw_o, val << 31);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
break;
}
} else if (is_privileged(ctx, 0)) {
@ -2084,7 +2084,7 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
}
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
break;
}
}

2
target/s390x/cpu_features.c
View File

@ -249,7 +249,7 @@ static void init_groups(void)
{
int i;
/* init all bitmaps from gnerated data initially */
/* init all bitmaps from generated data initially */
for (i = 0; i < ARRAY_SIZE(s390_feature_groups); i++) {
s390_init_feat_bitmap(s390_feature_groups[i].init,
s390_feature_groups[i].feat);

2
target/s390x/cpu_models.c
View File

@ -975,7 +975,7 @@ static void register_types(void)
init_ignored_base_feat();
/* init all bitmaps from gnerated data initially */
/* init all bitmaps from generated data initially */
s390_init_feat_bitmap(qemu_max_init, qemu_max_cpu_feat);
for (i = 0; i < ARRAY_SIZE(s390_cpu_defs); i++) {
s390_init_feat_bitmap(s390_cpu_defs[i].base_init,

2
target/s390x/tcg/fpu_helper.c
View File

@ -87,7 +87,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
/*
* FIXME:
* 1. Right now, all inexact conditions are inidicated as
* 1. Right now, all inexact conditions are indicated as
* "truncated" (0) and never as "incremented" (1) in the DXC.
* 2. Only traps due to invalid/divbyzero are suppressing. Other traps
* are completing, meaning the target register has to be written!

2
target/s390x/tcg/insn-data.h.inc
View File

@ -529,7 +529,7 @@
/* LOAD LOGICAL HALFWORD RELATIVE LONG */
C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
/* LOAD LOGICAL IMMEDATE */
/* LOAD LOGICAL IMMEDIATE */
D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)

2
target/s390x/tcg/translate.c
View File

@ -429,7 +429,7 @@ static void gen_exception(int excp)
static void gen_program_exception(DisasContext *s, int code)
{
/* Remember what pgm exeption this was. */
/* Remember what pgm exception this was. */
tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
offsetof(CPUS390XState, int_pgm_code));

14
target/sparc/asi.h
View File

@ -144,13 +144,13 @@
* ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
* and later ASIs.
*/
#define ASI_REAL 0x14 /* Real address, cachable */
#define ASI_REAL 0x14 /* Real address, cacheable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
#define ASI_REAL_IO 0x15 /* Real address, non-cachable */
#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
#define ASI_REAL_L 0x1c /* Real address, cachable, LE */
#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */
#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
@ -163,15 +163,15 @@
#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
* secondary, user
*/
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */
#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */
#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */
#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
#define ASI_TWINX_N 0x27 /* twin load, nucleus */
#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */
#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */
#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */
#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */
#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
@ -231,7 +231,7 @@
#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */

2
target/tricore/csfr.h.inc
View File

@ -1,4 +1,4 @@
/* A(ll) access permited
/* A(ll) access permitted
R(ead only) access
E(nd init protected) access

2
target/tricore/helper.c
View File

@ -57,7 +57,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return phys_addr;
}
/* TODO: Add exeption support*/
/* TODO: Add exception support */
static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
int rw, int tlb_error)
{

8
target/tricore/translate.c
View File

@ -128,7 +128,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
* Functions to generate micro-ops
*/
/* Makros for generating helpers */
/* Macros for generating helpers */
#define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
@ -336,8 +336,8 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
makros R, A and E, which allow read-only, all and endinit protected access.
These makros also specify in which ISA version the csfr was introduced. */
macros R, A and E, which allow read-only, all and endinit protected access.
These macros also specify in which ISA version the csfr was introduced. */
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
@ -362,7 +362,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
#undef E
#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
since no execption occurs */
since no exception occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \

4
tests/tcg/Makefile.target
View File

@ -120,7 +120,7 @@ endif
%: %.S
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
else
# For softmmu targets we include a different Makefile fragement as the
# For softmmu targets we include a different Makefile fragment as the
# build options for bare programs are usually pretty different. They
# are expected to provide their own build recipes.
EXTRA_CFLAGS += -ffreestanding
@ -154,7 +154,7 @@ PLUGINS=$(patsubst %.c, lib%.so, $(notdir $(wildcard $(PLUGIN_SRC)/*.c)))
# pre-requistes manually here as we can't use stems to handle it. We
# only expand MULTIARCH_TESTS which are common on most of our targets
# to avoid an exponential explosion as new tests are added. We also
# add some special helpers the run-plugin- rules can use bellow.
# add some special helpers the run-plugin- rules can use below.
ifneq ($(MULTIARCH_TESTS),)
$(foreach p,$(PLUGINS), \

2
tests/tcg/aarch64/gdbstub/test-sve.py
View File

@ -1,6 +1,6 @@
from __future__ import print_function
#
# Test the SVE registers are visable and changeable via gdbstub
# Test the SVE registers are visible and changeable via gdbstub
#
# This is launched via tests/guest-debug/run-test.py
#

2
tests/tcg/aarch64/sme-outprod1.c
View File

@ -28,7 +28,7 @@ asm(
" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
/*
* Read the first 4x4 sub-matrix of elements from tile 1:
* Note that za1h should be interchangable here.
* Note that za1h should be interchangeable here.
*/
" mov w12, #0\n"
" mova z0.s, p0/m, za1v.s[w12, #0]\n"

6
tests/tcg/aarch64/system/boot.S
View File

@ -9,7 +9,7 @@
/*
* Semihosting interface on ARM AArch64
* See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM
* See "Semihosting for AArch32 and AArch64 Release 2.0" by ARM
* w0 - semihosting call number
* x1 - semihosting parameter
*/
@ -147,7 +147,7 @@ __start:
* T0SZ[5:0] = 2^(64 - 25)
*
* The size of T0SZ controls what the initial lookup level. It
* would be nice to start at level 2 but unfortunatly for a
* would be nice to start at level 2 but unfortunately for a
* flat-mapping on the virt machine we need to handle IA's
* with at least 1gb range to see RAM. So we start with a
* level 1 lookup.
@ -189,7 +189,7 @@ __start:
msr cpacr_el1, x0
/* Setup some stack space and enter the test code.
* Assume everthing except the return value is garbage when we
* Assume everything except the return value is garbage when we
* return, we won't need it.
*/
adrp x0, stack_end

2
tests/tcg/aarch64/system/semiheap.c
View File

@ -86,7 +86,7 @@ int main(int argc, char *argv[argc])
}
ptr_to_heap++;
}
ml_printf("r/w to heap upto %p\n", ptr_to_heap);
ml_printf("r/w to heap up to %p\n", ptr_to_heap);
ml_printf("Passed HeapInfo checks\n");
return 0;

2
tests/tcg/multiarch/sha512.c
View File

@ -453,7 +453,7 @@ void sha512(struct sha512 *sha, const void *p, size_t size)
/* From hex.h */
/**
* hex_decode - Unpack a hex string.
* @str: the hexidecimal string
* @str: the hexadecimal string
* @slen: the length of @str
* @buf: the buffer to write the data into
* @bufsize: the length of @buf

2
tests/tcg/multiarch/system/Makefile.softmmu-target
View File

@ -3,7 +3,7 @@
# Multiarch system tests
#
# We just collect the tests together here and rely on the actual guest
# architecture to add to the test dependancies and deal with the
# architecture to add to the test dependencies and deal with the
# complications of building.
#

2
tests/tcg/s390x/mvc.c
View File

@ -85,7 +85,7 @@ int main(void)
}
}
/* test if MVC works now correctly accross page boundaries */
/* test if MVC works now correctly across page boundaries */
mvc_256(dst + 4096 - 128, src + 4096 - 128);
for (i = 0; i < ALLOC_SIZE; i++) {
if (src[i] != 0xff) {

4
tests/tcg/tricore/c/crt0-tc2x.S
View File

@ -263,7 +263,7 @@ __copy_table_next:
ld.w %d3,[%a13+]4 # %d3 = block length
jeq %d3,-1,__copy_table_done # length == -1 => end of table
sh %d0,%d3,-3 # %d0 = length / 8 (doublewords)
and %d1,%d3,7 # %d1 = lenght % 8 (rem. bytes)
and %d1,%d3,7 # %d1 = length % 8 (rem. bytes)
jz %d0,__copy_word # block size < 8 => copy word
addi %d0,%d0,-1 # else doublewords -= 1
mov.a %a2,%d0 # %a2 = loop counter
@ -274,7 +274,7 @@ __copy_dword:
__copy_word:
jz %d1,__copy_table_next
sh %d0,%d1,-2 # %d0 = length / 4 (words)
and %d1,%d1,3 # %d1 = lenght % 4 (rem. bytes)
and %d1,%d1,3 # %d1 = length % 4 (rem. bytes)
jz %d0,__copy_hword # block size < 4 => copy hword
ld.w %d14,[%a15+]4 # copy one word
st.w [%a14+]4,%d14

4
tests/tcg/x86_64/system/boot.S
View File

@ -121,7 +121,7 @@ _start:
// Setup stack ASAP
movq $stack_end,%rsp
/* don't worry about stack frame, assume everthing is garbage when we return */
/* don't worry about stack frame, assume everything is garbage when we return */
call main
_exit: /* output any non-zero result in eax to isa-debug-exit device */
@ -195,7 +195,7 @@ idt_1F: .int 0, 0
*
* This describes various memory areas (segments) through
* segment descriptors. In 32 bit mode each segment each
* segement is associated with segment registers which are
* segment is associated with segment registers which are
* implicitly (or explicitly) referenced depending on the
* instruction. However in 64 bit mode selectors are flat and
* segmented addressing isn't used.