qemu/riscv at 27c22b2de08f71500df581563cc9d22638a14b4d - qemu

History

Bin Meng 27c22b2de0 hw/riscv: microchip_pfsoc: Map the reserved memory at address 0

Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.

[1] See the config_copy() calls in various places in ddr_setup() in
    the HSS source codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2020-11-03 07:17:23 -08:00

boot_opensbi.h

riscv: Add opensbi firmware dynamic support

2020-07-13 17:25:37 -07:00

boot.h

hw/riscv: Load the kernel after the firmware

2020-10-22 12:00:22 -07:00

microchip_pfsoc.h

hw/riscv: microchip_pfsoc: Map the reserved memory at address 0

2020-11-03 07:17:23 -08:00

numa.h

hw/riscv: Add helpers for RISC-V multi-socket NUMA machines