qemu/target/arm
Peter Maydell 25489b521b target/arm: LDAPR should honour SCTLR_ELx.nAA
In commit c1a1f80518 when we added the FEAT_LSE2 relaxations to
the alignment requirements for atomic and ordered loads and stores,
we didn't quite get it right for LDAPR/LDAPRH/LDAPRB with no
immediate offset.  These instructions were handled in the old decoder
as part of disas_ldst_atomic(), but unlike all the other insns that
function decoded (LDADD, LDCLR, etc) these insns are "ordered", not
"atomic", so they should be using check_ordered_align() rather than
check_atomic_align().  Commit c1a1f80518 used
check_atomic_align() regardless for everything in
disas_ldst_atomic().  We then carried that incorrect check over in
the decodetree conversion, where LDAPR/LDAPRH/LDAPRB are now handled
by trans_LDAPR().

The effect is that when FEAT_LSE2 is implemented, these instructions
don't honour the SCTLR_ELx.nAA bit and will generate alignment
faults when they should not.

(The LDAPR insns with an immediate offset were in disas_ldst_ldapr_stlr()
and then in trans_LDAPR_i() and trans_STLR_i(), and have always used
the correct check_ordered_align().)

Use check_ordered_align() in trans_LDAPR().

Cc: qemu-stable@nongnu.org
Fixes: c1a1f80518 ("target/arm: Relax ordered/atomic alignment checks for LSE2")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240709134504.3500007-3-peter.maydell@linaro.org
2024-07-18 13:49:28 +01:00
..
hvf gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
tcg target/arm: LDAPR should honour SCTLR_ELx.nAA 2024-07-18 13:49:28 +01:00
arch_dump.c
arm-powerctl.c
arm-powerctl.h
arm-qmp-cmds.c target: Improve error reporting for CpuModelInfo member @props 2024-03-12 14:03:00 +01:00
common-semi-target.h
cortex-regs.c
cpregs.h
cpu64.c target/arm: Replace sprintf() by snprintf() 2024-06-04 10:02:39 +02:00
cpu-features.h target/arm: Implement FEAT WFxT and enable for '-cpu max' 2024-05-30 16:35:17 +01:00
cpu-param.h target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h' 2024-04-26 15:31:37 +02:00
cpu-qom.h target/arm: Add support for Non-maskable Interrupt 2024-04-25 10:21:04 +01:00
cpu.c target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() 2024-07-11 11:41:34 +01:00
cpu.h target/arm: Use cpu_env in cpu_untagged_addr 2024-07-11 11:41:33 +01:00
debug_helper.c
gdbstub64.c gdbstub: Add support for MTE in user mode 2024-07-05 12:35:33 +01:00
gdbstub.c gdbstub: Add support for MTE in user mode 2024-07-05 12:35:33 +01:00
gtimer.h target/arm: Move GTimer definitions to new 'gtimer.h' header 2024-01-26 11:30:49 +00:00
helper.c target/arm: Implement FEAT WFxT and enable for '-cpu max' 2024-05-30 16:35:17 +01:00
helper.h target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree 2024-07-01 15:40:52 +01:00
hvf_arm.h
hyp_gdbstub.c gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
idau.h
internals.h target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() 2024-07-11 11:41:34 +01:00
Kconfig kconfig: express dependency of individual boards on libfdt 2024-05-10 15:45:15 +02:00
kvm_arm.h
kvm-consts.h exec: Rename NEED_CPU_H -> COMPILING_PER_TARGET 2024-04-26 09:49:51 +02:00
kvm-stub.c
kvm.c gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
machine.c target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically 2024-07-11 11:41:33 +01:00
meson.build target/arm: Move v7m-related code from cpu32.c into a separate file 2024-03-08 14:45:03 +00:00
multiprocessing.h
op_addsub.h
ptw.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
syndrome.h target/arm: fix exception syndrome for AArch32 bkpt insn 2024-02-02 13:51:57 +00:00
tcg-stubs.c
trace-events target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling 2024-03-07 12:19:03 +00:00
trace.h
vfp_helper.c target/arm: Allow FPCR bits that aren't in FPSCR 2024-07-11 11:41:33 +01:00