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qemu/target/riscv
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Anup Patel 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode 
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-05-24 10:38:50 +10:00
..
insn_trans
target/riscv: rvv: Fix early exit condition for whole register load/store
2022-05-24 09:48:20 +10:00
arch_dump.c
…
bitmanip_helper.c
target/riscv: rvk: add support for zbkx extension
2022-04-29 10:47:45 +10:00
cpu_bits.h
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
cpu_helper.c
target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
2022-05-24 10:38:50 +10:00
cpu_user.h
…
cpu-param.h
Normalize header guard symbol definition
2022-05-11 16:50:26 +02:00
cpu.c
target/riscv: Fix typo of mimpid cpu option
2022-05-24 10:38:50 +10:00
cpu.h
target/riscv: Fix typo of mimpid cpu option
2022-05-24 10:38:50 +10:00
crypto_helper.c
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
csr.c
target/riscv: Fix csr number based privilege checking
2022-05-24 10:38:50 +10:00
debug.c
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
debug.h
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
fpu_helper.c
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
gdbstub.c
target/riscv: correct "code should not be reached" for x-rv128
2022-02-16 12:24:18 +10:00
helper.h
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
insn16.decode
…
insn32.decode
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
instmap.h
…
internals.h
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
Kconfig
…
kvm_riscv.h
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm-stub.c
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm.c
Remove qemu-common.h include from most units
2022-04-06 14:31:55 +02:00
m128_helper.c
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
machine.c
target/riscv: machine: Add debug state description
2022-04-22 10:35:16 +10:00
meson.build
target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-04-29 10:47:45 +10:00
monitor.c
target/riscv: Fix incorrect PTE merge in walk_pte
2022-04-29 10:47:46 +10:00
op_helper.c
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
pmp.c
target/riscv/pmp: fix NAPOT range computation overflow
2022-04-22 10:35:16 +10:00
pmp.h
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h
Clean up ill-advised or unusual header guards
2022-05-11 16:50:01 +02:00
trace-events
…
trace.h
…
translate.c
target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-04-29 10:47:45 +10:00
vector_helper.c
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-04-22 10:35:16 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00