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Hongren (Zenithal) Zheng 5160bacc06 target/riscv: add zicsr/zifencei to isa_string 
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-05-24 10:38:50 +10:00
..
insn_trans
target/riscv: rvv: Fix early exit condition for whole register load/store
2022-05-24 09:48:20 +10:00
arch_dump.c
…
bitmanip_helper.c
target/riscv: rvk: add support for zbkx extension
2022-04-29 10:47:45 +10:00
cpu_bits.h
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
cpu_helper.c
target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
2022-05-24 10:38:50 +10:00
cpu_user.h
…
cpu-param.h
Normalize header guard symbol definition
2022-05-11 16:50:26 +02:00
cpu.c
target/riscv: add zicsr/zifencei to isa_string
2022-05-24 10:38:50 +10:00
cpu.h
target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
2022-05-24 10:38:50 +10:00
crypto_helper.c
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
csr.c
target/riscv: Fix csr number based privilege checking
2022-05-24 10:38:50 +10:00
debug.c
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
debug.h
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
fpu_helper.c
…
gdbstub.c
…
helper.h
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
insn16.decode
…
insn32.decode
target/riscv: rvk: add support for zksed/zksh extension
2022-04-29 10:47:45 +10:00
instmap.h
…
internals.h
…
Kconfig
…
kvm_riscv.h
…
kvm-stub.c
…
kvm.c
…
m128_helper.c
…
machine.c
target/riscv: machine: Add debug state description
2022-04-22 10:35:16 +10:00
meson.build
target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-04-29 10:47:45 +10:00
monitor.c
target/riscv: Fix incorrect PTE merge in walk_pte
2022-04-29 10:47:46 +10:00
op_helper.c
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
pmp.c
target/riscv/pmp: fix NAPOT range computation overflow
2022-04-22 10:35:16 +10:00
pmp.h
target/riscv: rvk: add CSR support for Zkr
2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h
Clean up ill-advised or unusual header guards
2022-05-11 16:50:01 +02:00
trace-events
…
trace.h
…
translate.c
target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
2022-05-24 10:38:50 +10:00
vector_helper.c
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-04-22 10:35:16 +10:00
XVentanaCondOps.decode
…