1d1ee55274
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> |
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cpu_bits.h | ||
cpu_user.h | ||
cpu.c | ||
cpu.h | ||
fpu_helper.c | ||
gdbstub.c | ||
helper.c | ||
helper.h | ||
instmap.h | ||
Makefile.objs | ||
op_helper.c | ||
pmp.c | ||
pmp.h | ||
translate.c |