RISC-V: Update E and I extension order
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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@ -26,7 +26,7 @@
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/* RISC-V CPU definitions */
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static const char riscv_exts[26] = "IMAFDQECLBJTPVNSUHKORWXYZG";
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static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
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const char * const riscv_int_regnames[] = {
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"zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ",
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@ -71,6 +71,7 @@
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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