c2e6d7d8e7
QEMU populates the apic_state attribute of x86 CPUs if supported by real
hardware or if SMP is active. When handling interrupts, it just checks whether
apic_state is populated to route the interrupt to the PIC or to the APIC.
However, chapter 10.4.3 of [1] requires that:
When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
IA-32 processor without an on-chip APIC.
This means that when apic_state is populated, QEMU needs to check for the
MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some
real-world BIOSes.
[1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:
System Programming Guide, Part 1
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240106132546.21248-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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|---|---|---|
| .. | ||
| apic_internal.h | ||
| apic-msidef.h | ||
| apic.h | ||
| hostmem-epc.h | ||
| intel_iommu.h | ||
| microvm.h | ||
| pc.h | ||
| sgx-epc.h | ||
| topology.h | ||
| vmport.h | ||
| x86-iommu.h | ||
| x86.h | ||
| xen_arch_hvm.h | ||