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hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled

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QEMU populates the apic_state attribute of x86 CPUs if supported by real
hardware or if SMP is active. When handling interrupts, it just checks whether
apic_state is populated to route the interrupt to the PIC or to the APIC.
However, chapter 10.4.3 of [1] requires that:

  When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
  IA-32 processor without an on-chip APIC.

This means that when apic_state is populated, QEMU needs to check for the
MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some
real-world BIOSes.

[1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:
    System Programming Guide, Part 1

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240106132546.21248-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2024-01-06 14:25:45 +01:00 committed by Michael S. Tsirkin
parent f22f3a92eb
commit c2e6d7d8e7
3 changed files with 16 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/i386/x86.c
View File

@ -520,7 +520,7 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
CPU_FOREACH(cs) {
X86CPU *cpu = X86_CPU(cs);
if (cpu->apic_state) {
if (cpu_is_apic_enabled(cpu->apic_state)) {
apic_deliver_nmi(cpu->apic_state);
} else {
cpu_interrupt(cs, CPU_INTERRUPT_NMI);
@ -555,7 +555,7 @@ static void pic_irq_request(void *opaque, int irq, int level)
X86CPU *cpu = X86_CPU(cs);
trace_x86_pic_interrupt(irq, level);
if (cpu->apic_state && !kvm_irqchip_in_kernel() &&
if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() &&
!whpx_apic_in_platform()) {
CPU_FOREACH(cs) {
cpu = X86_CPU(cs);

13
hw/intc/apic_common.c
View File

@ -62,6 +62,19 @@ uint64_t cpu_get_apic_base(DeviceState *dev)
}
}
bool cpu_is_apic_enabled(DeviceState *dev)
{
APICCommonState *s;
if (!dev) {
return false;
}
s = APIC_COMMON(dev);
return s->apicbase & MSR_IA32_APICBASE_ENABLE;
}
void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
{
APICCommonState *s;

1
include/hw/i386/apic.h
View File

@ -10,6 +10,7 @@ void apic_deliver_nmi(DeviceState *d);
int apic_get_interrupt(DeviceState *s);
int cpu_set_apic_base(DeviceState *s, uint64_t val);
uint64_t cpu_get_apic_base(DeviceState *s);
bool cpu_is_apic_enabled(DeviceState *s);
void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
uint8_t cpu_get_apic_tpr(DeviceState *s);
void apic_init_reset(DeviceState *s);