Ivan Klokov 1a25e59c62 target/riscv: pmp: Ignore writes when RW=01 and MML=0 ... This patch changes behavior on writing RW=01 to pmpcfg with MML=0. RWX filed is form of collective WARL with the combination of pmpcfg.RW=01 remains reserved for future standard use. According to definition of WARL writing the CSR has no other side effect. But current implementation change architectural state and change system behavior. After writing we will get unreadable-unwriteble region regardless on the previous state. On the other side WARL said that we should read legal value and nothing says about what we should write. Current behavior change system state regardless of whether we read this register or not. Fixes: ac66f2f0 ("target/riscv: pmp: Ignore writes when RW=01") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231220153205.11072-1-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-01-10 18:47:47 +10:00
..
insn_trans	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
kvm	target/riscv/kvm: add RVV and Vector CSR regs	2024-01-10 18:47:47 +10:00
tcg	target/riscv: add 'parent' in profile description	2024-01-10 18:47:47 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_cfg.h	target/riscv: implement svade	2024-01-10 18:47:47 +10:00
cpu_helper.c	qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD	2024-01-08 10:45:43 -05:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rva22s64 cpu	2024-01-10 18:47:47 +10:00
cpu.c	target/riscv: add rva22s64 cpu	2024-01-10 18:47:47 +10:00
cpu.h	target/riscv: add 'parent' in profile description	2024-01-10 18:47:47 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: Not allow write mstatus_vs without RVV	2024-01-10 18:47:46 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c
gdbstub.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
machine.c	target/riscv: Constify VMState in machine.c	2023-12-29 11:17:30 +11:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c
op_helper.c
pmp.c	target/riscv: pmp: Ignore writes when RW=01 and MML=0	2024-01-10 18:47:47 +10:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Use existing PMU counter mask in FDT generation	2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	target/riscv: Fix vfwmaccbf16.vf	2023-10-12 12:50:13 +10:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c