Atish Patra 18d6d89efc target/riscv: pmu: Make number of counters configurable ... The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-07-03 10:03:20 +10:00
..
insn_trans	target/riscv: Minimize the calls to decode_save_opc	2022-07-03 10:03:20 +10:00
arch_dump.c
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
cpu_helper.c	semihosting: Return void from do_common_semihosting	2022-06-28 04:35:07 +05:30
cpu_user.h
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: pmu: Make number of counters configurable	2022-07-03 10:03:20 +10:00
cpu.h	target/riscv: pmu: Make number of counters configurable	2022-07-03 10:03:20 +10:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: pmu: Make number of counters configurable	2022-07-03 10:03:20 +10:00
debug.c	target/riscv/debug.c: keep experimental rv128 support working	2022-06-10 09:31:42 +10:00
debug.h	target/riscv: csr: Hook debug CSR read/write	2022-04-22 10:35:16 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c	target/riscv: correct "code should not be reached" for x-rv128	2022-02-16 12:24:18 +10:00
helper.h	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
insn16.decode	target/riscv: accessors to registers upper part and 128-bit load/store	2022-01-08 15:46:10 +10:00
insn32.decode	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
instmap.h
internals.h	target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions	2022-06-10 09:31:42 +10:00
Kconfig
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	Remove qemu-common.h include from most units	2022-04-06 14:31:55 +02:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: machine: Add debug state description	2022-04-22 10:35:16 +10:00
meson.build	target/riscv: rvk: add support for zknd/zkne extension in RV32	2022-04-29 10:47:45 +10:00
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmp.c	target/riscv/pmp: guard against PMP ranges with a negative size	2022-07-03 10:03:20 +10:00
pmp.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
trace-events
trace.h
translate.c	target/riscv: Minimize the calls to decode_save_opc	2022-07-03 10:03:20 +10:00
vector_helper.c	target/riscv: rvv: Add tail agnostic for vector permutation instructions	2022-06-10 09:31:42 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00