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qemu/hw/pci-bridge
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Jonathan Cameron 314f5033c6 hw/pci-bridge/cxl_downstream: Set default link width and link speed 
Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07 03:39:11 -05:00
..
cxl_downstream.c
hw/pci-bridge/cxl_downstream: Set default link width and link speed
2023-11-07 03:39:11 -05:00
cxl_root_port.c
hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
2023-11-07 03:39:11 -05:00
cxl_upstream.c
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
2023-11-07 03:39:11 -05:00
gen_pcie_root_port.c
pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-cap
2023-01-28 06:21:29 -05:00
i82801b11.c
hw: Move ich9.h to southbridge/
2023-02-27 22:29:01 +01:00
ioh3420.c
…
Kconfig
hw/pci-bridge: make building pcie-to-pci bridge configurable
2023-05-19 10:30:46 -04:00
meson.build
meson: Replace softmmu_ss -> system_ss
2023-06-20 10:01:30 +02:00
pci_bridge_dev.c
pci_bridge: remove whitespace
2023-01-28 06:21:29 -05:00
pci_expander_bridge_stubs.c
…
pci_expander_bridge.c
hw/pci: spelling fixes
2023-09-20 07:54:34 +03:00
pcie_pci_bridge.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
pcie_root_port.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
simba.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
xio3130_downstream.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
xio3130_upstream.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00