Jonathan Cameron 0b4aec2469 CXL/cxl_component: Add cxl_get_hb_cstate() ...

Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.

Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-32-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

2022-05-13 07:57:26 -04:00

..

cxl_root_port.c

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

dec.c

…

dec.h

…

gen_pcie_root_port.c

hw/pcie-root-port: Fix hotplug for PCI devices requiring IO

2021-08-03 16:31:07 -04:00

i82801b11.c

…

ioh3420.c

…

Kconfig

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

meson.build

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

pci_bridge_dev.c

…

pci_expander_bridge.c

CXL/cxl_component: Add cxl_get_hb_cstate()

2022-05-13 07:57:26 -04:00

pcie_pci_bridge.c

…

pcie_root_port.c

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

simba.c

…

xio3130_downstream.c

pci: expose TYPE_XIO3130_DOWNSTREAM name

2022-03-06 05:08:23 -05:00

xio3130_upstream.c

pci-bridge/xio3130_upstream: Fix error handling

2022-03-06 05:08:23 -05:00