qemu/target
Alexandre Ghiti 6df3747a27
riscv: Introduce satp mode hw capabilities
Currently, the max satp mode is set with the only constraint that it must be
implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].

But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode which is incompatible with the cpu's sv39 max
capability.

So add a new bitmap to RISCVSATPMap which contains this capability and
initialize it in every XXX_cpu_init.

Finally:
- valid_vm_1_10_[32|64] constrains which satp mode the CPU can use
- the CPU hw capabilities constrains what the user may select
- the user's selection then constrains what's available to the guest
  OS.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230303131252.892893-5-alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06 08:09:43 -08:00
..
alpha accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
arm Monitor patches for 2023-03-02 2023-03-02 10:54:17 +00:00
avr accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
cris target/cris: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
hexagon target/hexagon/idef-parser: Drop gen_tmp_local 2023-03-01 07:33:28 -10:00
hppa target/hppa: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
i386 * bugfixes 2023-03-02 16:13:45 +00:00
loongarch target/loongarch: Implement Chip Configuraiton Version Register(0x0000) 2023-03-03 09:37:30 +08:00
m68k accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
microblaze accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
mips target/mips: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
nios2 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
openrisc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
ppc target/ppc/translate: Add dummy implementation for dcblc instruction 2023-03-03 16:50:17 -03:00
riscv riscv: Introduce satp mode hw capabilities 2023-03-06 08:09:43 -08:00
rx accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
s390x accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sh4 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sparc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
tricore accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
xtensa target/xtensa: Don't use tcg_temp_local_new_* 2023-03-01 07:33:28 -10:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00