qemu/hw/riscv
Bin Meng 143897b501 hw/riscv: microchip_pfsoc: Support direct kernel boot
At present the Microchip Icicle Kit machine only supports using
'-bios' to load the HSS, and does not support '-kernel' for direct
kernel booting just like other RISC-V machines do. One has to use
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
This is not so convenient.

Adding '-kernel' support together with the existing '-bios', we
follow the following table to select which payload we execute:

  -bios |    -kernel | payload
  ------+------------+--------
      N |          N | HSS
      Y | don't care | HSS
      N |          Y | kernel

This ensures backwards compatibility with how we used to expose
'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
must be present to provide a valid device tree for the board,
as we don't generate device tree.

When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
is used to boot a payload like U-Boot or OS kernel directly.

Documentation is updated to describe the direct kernel boot. Note
as of today there is still no PolarFire SoC support in the upstream
Linux kernel hence the document does not include instructions for
that. It will be updated in the future.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:42 +10:00
..
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
Kconfig hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine 2021-05-11 20:02:06 +10:00
meson.build riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
microchip_pfsoc.c hw/riscv: microchip_pfsoc: Support direct kernel boot 2021-06-08 09:59:42 +10:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: Fix OT IBEX reset vector 2021-05-11 20:02:07 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_e.c hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] 2021-05-11 20:01:10 +10:00
sifive_u.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00
spike.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00
virt.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00