mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: Add initial support for Shakti C machine

Browse Source 
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.

https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
[Changes by AF:
 - Check for mstate->firmware before loading it
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Vijai Kumar K 2021-04-01 23:44:55 +05:30 committed by Alistair Francis
parent 6ddc7069f5
commit 7a261bafc8
6 changed files with 265 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -1415,6 +1415,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
Shakti C class SoC
M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/shakti_c.c
F: include/hw/riscv/shakti_c.h
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>

1
default-configs/devices/riscv64-softmmu.mak
View File

@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
CONFIG_MICROCHIP_PFSOC=y
CONFIG_SHAKTI_C=y

10
hw/riscv/Kconfig
View File

@ -19,6 +19,16 @@ config OPENTITAN
select IBEX
select UNIMP
config SHAKTI
bool
config SHAKTI_C
bool
select UNIMP
select SHAKTI
select SIFIVE_CLINT
select SIFIVE_PLIC
config RISCV_VIRT
bool
imply PCI_DEVICES

1
hw/riscv/meson.build
View File

@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))

173
hw/riscv/shakti_c.c Normal file
View File

@ -0,0 +1,173 @@
/*
* Shakti C-class SoC emulation
*
* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/boards.h"
#include "hw/riscv/shakti_c.h"
#include "qapi/error.h"
#include "hw/intc/sifive_plic.h"
#include "hw/intc/sifive_clint.h"
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "hw/riscv/boot.h"
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} shakti_c_memmap[] = {
[SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
[SHAKTI_C_RAM] = { 0x80000000, 0x0 },
[SHAKTI_C_UART] = { 0x00011300, 0x00040 },
[SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
[SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
[SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
[SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
};
static void shakti_c_machine_state_init(MachineState *mstate)
{
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
/* Allow only Shakti C CPU for this platform */
if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
error_report("This board can only be used with Shakti C CPU");
exit(1);
}
/* Initialize SoC */
object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
TYPE_RISCV_SHAKTI_SOC);
qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
mstate->ram_size, &error_fatal);
memory_region_add_subregion(system_memory,
shakti_c_memmap[SHAKTI_C_RAM].base,
main_mem);
/* ROM reset vector */
riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
shakti_c_memmap[SHAKTI_C_RAM].base,
shakti_c_memmap[SHAKTI_C_ROM].base,
shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
NULL);
if (mstate->firmware) {
riscv_load_firmware(mstate->firmware,
shakti_c_memmap[SHAKTI_C_RAM].base,
NULL);
}
}
static void shakti_c_machine_instance_init(Object *obj)
{
}
static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
{
MachineClass *mc = MACHINE_CLASS(klass);
mc->desc = "RISC-V Board compatible with Shakti SDK";
mc->init = shakti_c_machine_state_init;
mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
}
static const TypeInfo shakti_c_machine_type_info = {
.name = TYPE_RISCV_SHAKTI_MACHINE,
.parent = TYPE_MACHINE,
.class_init = shakti_c_machine_class_init,
.instance_init = shakti_c_machine_instance_init,
.instance_size = sizeof(ShaktiCMachineState),
};
static void shakti_c_machine_type_info_register(void)
{
type_register_static(&shakti_c_machine_type_info);
}
type_init(shakti_c_machine_type_info_register)
static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
{
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
MemoryRegion *system_memory = get_system_memory();
sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
SHAKTI_C_PLIC_NUM_SOURCES,
SHAKTI_C_PLIC_NUM_PRIORITIES,
SHAKTI_C_PLIC_PRIORITY_BASE,
SHAKTI_C_PLIC_PENDING_BASE,
SHAKTI_C_PLIC_ENABLE_BASE,
SHAKTI_C_PLIC_ENABLE_STRIDE,
SHAKTI_C_PLIC_CONTEXT_BASE,
SHAKTI_C_PLIC_CONTEXT_STRIDE,
shakti_c_memmap[SHAKTI_C_PLIC].size);
sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
memory_region_add_subregion(system_memory,
shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
}
static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = shakti_c_soc_state_realize;
}
static void shakti_c_soc_instance_init(Object *obj)
{
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
/*
* CPU type is fixed and we are not supporting passing from commandline yet.
* So let it be in instance_init. When supported should use ms->cpu_type
* instead of TYPE_RISCV_CPU_SHAKTI_C
*/
object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
&error_abort);
}
static const TypeInfo shakti_c_type_info = {
.name = TYPE_RISCV_SHAKTI_SOC,
.parent = TYPE_DEVICE,
.class_init = shakti_c_soc_class_init,
.instance_init = shakti_c_soc_instance_init,
.instance_size = sizeof(ShaktiCSoCState),
};
static void shakti_c_type_info_register(void)
{
type_register_static(&shakti_c_type_info);
}
type_init(shakti_c_type_info_register)

73
include/hw/riscv/shakti_c.h Normal file
View File

@ -0,0 +1,73 @@
/*
* Shakti C-class SoC emulation
*
* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SHAKTI_H
#define HW_SHAKTI_H
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
typedef struct ShaktiCSoCState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
MemoryRegion rom;
} ShaktiCSoCState;
#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
#define RISCV_SHAKTI_MACHINE(obj) \
OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
typedef struct ShaktiCMachineState {
/*< private >*/
MachineState parent_obj;
/*< public >*/
ShaktiCSoCState soc;
} ShaktiCMachineState;
enum {
SHAKTI_C_ROM,
SHAKTI_C_RAM,
SHAKTI_C_UART,
SHAKTI_C_GPIO,
SHAKTI_C_PLIC,
SHAKTI_C_CLINT,
SHAKTI_C_I2C,
};
#define SHAKTI_C_PLIC_HART_CONFIG "MS"
/* Including Interrupt ID 0 (no interrupt)*/
#define SHAKTI_C_PLIC_NUM_SOURCES 28
/* Excluding Priority 0 */
#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
#endif