qemu/tcg/riscv
Richard Henderson 12fde9bcdb tcg: Add INDEX_op_qemu_{ld,st}_i128
Add opcodes for backend support for 128-bit memory operations.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16 16:30:25 -07:00
..
tcg-target-con-set.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target-con-str.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target.c.inc tcg: Introduce tcg_target_has_memory_bswap 2023-05-16 15:21:39 -07:00
tcg-target.h tcg: Add INDEX_op_qemu_{ld,st}_i128 2023-05-16 16:30:25 -07:00