faee5441a0
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram address within 3GB, but not all platforms have dram_base within 3GB. This patch adds an exception for dram base not within 3GB, which will place fdt at dram_end align 16MB. riscv_setup_rom_reset_vec() also needs to be modified Signed-off-by: Dylan Jhong <dylan@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220419115945.37945-1-dylan@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| .. | ||
| boot_opensbi.h | ||
| boot.h | ||
| microchip_pfsoc.h | ||
| numa.h | ||
| opentitan.h | ||
| riscv_hart.h | ||
| shakti_c.h | ||
| sifive_cpu.h | ||
| sifive_e.h | ||
| sifive_u.h | ||
| spike.h | ||
| virt.h | ||