Bin Meng 1237c2d694 hw/char: riscv_htif: Move registers from CPUArchState to HTIFState ... At present for some unknown reason the HTIF registers (fromhost & tohost) are defined in the RISC-V CPUArchState. It should really be put in the HTIFState struct as it is only meaningful to HTIF. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-20 10:14:13 +10:00
..
boot.c	riscv: re-randomize rng-seed on reboot	2022-10-27 11:34:31 +01:00
Kconfig	hw/riscv: Sort machines Kconfig options in alphabetical order	2023-01-06 10:42:55 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/{misc, riscv}: pfsoc: add system controller as unimplemented	2023-01-06 10:42:55 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization	2023-01-06 10:42:55 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
sifive_e.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
sifive_u.c	hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"	2023-01-06 10:42:55 +10:00
spike.c	hw/char: riscv_htif: Move registers from CPUArchState to HTIFState	2023-01-20 10:14:13 +10:00
virt.c	hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb	2023-01-06 10:42:55 +10:00