Alistair Francis 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 ... When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside tcg_gen_gvec_dup_i32(). This patch checks that condition and instead uses tcg_gen_gvec_dup_i64() is required. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028 Suggested-by: Robert Bu <robert.bu@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-06-10 09:42:12 +10:00
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trans_privileged.c.inc
trans_rva.c.inc
trans_rvb.c.inc	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
trans_rvd.c.inc
trans_rvf.c.inc
trans_rvh.c.inc
trans_rvi.c.inc
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2022-06-10 09:31:42 +10:00
trans_rvv.c.inc	target/riscv: trans_rvv: Avoid assert for RV32 and e64	2022-06-10 09:42:12 +10:00
trans_rvzfh.c.inc
trans_svinval.c.inc
trans_xventanacondops.c.inc