Anup Patel 10b43754cf hw/riscv: sifive_u: Add UART1 DT node in the generated DTB ... The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201111094725.3768755-1-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-12-17 21:56:43 -08:00
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boot.c	vl: extract softmmu/datadir.c	2020-12-10 12:15:18 -05:00
Kconfig	hw/riscv: microchip_pfsoc: Connect the SYSREG module	2020-11-03 07:17:23 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: Hook the I2C1 controller	2020-11-03 07:17:23 -08:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
sifive_u.c	hw/riscv: sifive_u: Add UART1 DT node in the generated DTB	2020-12-17 21:56:43 -08:00
spike.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
virt.c	vl: make qemu_get_machine_opts static	2020-12-15 12:51:55 -05:00