5decd2c521
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note the irq number calculation in sifive_plic_{read,write} is
correct as the codes make up for the irq number by adding 1.
Let's simply update "priority-base" to start from interrupt source
0 and add a comment to make it crystal clear.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-14-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
||
|---|---|---|
| .. | ||
| boot_opensbi.h | ||
| boot.h | ||
| microchip_pfsoc.h | ||
| numa.h | ||
| opentitan.h | ||
| riscv_hart.h | ||
| shakti_c.h | ||
| sifive_cpu.h | ||
| sifive_e.h | ||
| sifive_u.h | ||
| spike.h | ||
| virt.h | ||