Alistair Francis 094b072c68 target/riscv: cpu: Set XLEN independently from target ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com		2020-12-17 21:56:44 -08:00
..
insn_trans	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
cpu_bits.h	target/riscv: csr: Remove compile time XLEN checks	2020-12-17 21:56:44 -08:00
cpu_helper.c	target/riscv: cpu_helper: Remove compile time XLEN checks	2020-12-17 21:56:44 -08:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: cpu: Set XLEN independently from target	2020-12-17 21:56:44 -08:00
cpu.h	target/riscv: Add a riscv_cpu_is_32bit() helper function	2020-12-17 21:56:44 -08:00
csr.c	target/riscv: csr: Remove compile time XLEN checks	2020-12-17 21:56:44 -08:00
fpu_helper.c	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
insn16-32.decode
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Add V extension state description	2020-11-03 07:17:23 -08:00
meson.build	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
pmp.c	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
pmp.h	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Remove the hyp load and store functions	2020-11-09 15:08:57 -08:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00