target/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis
parent
f08c7ff3dc
commit
8987cdc481
@ -437,9 +437,7 @@
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#define HSTATUS_VGEIN 0x0003F000
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#define HSTATUS_VTVM 0x00100000
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#define HSTATUS_VTSR 0x00400000
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#if defined(TARGET_RISCV64)
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#define HSTATUS_VSXL 0x300000000
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#endif
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#define HSTATUS_VSXL 0x300000000
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#define HSTATUS32_WPRI 0xFF8FF87E
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#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
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@ -102,44 +102,65 @@ static int ctr(CPURISCVState *env, int csrno)
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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#if defined(TARGET_RISCV32)
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case CSR_CYCLEH:
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if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
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get_field(env->mcounteren, HCOUNTEREN_CY)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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if (riscv_cpu_is_32bit(env)) {
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switch (csrno) {
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case CSR_CYCLEH:
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if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
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get_field(env->mcounteren, HCOUNTEREN_CY)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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case CSR_TIMEH:
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if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
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get_field(env->mcounteren, HCOUNTEREN_TM)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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case CSR_INSTRETH:
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if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
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get_field(env->mcounteren, HCOUNTEREN_IR)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
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if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
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get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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}
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break;
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case CSR_TIMEH:
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if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
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get_field(env->mcounteren, HCOUNTEREN_TM)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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case CSR_INSTRETH:
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if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
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get_field(env->mcounteren, HCOUNTEREN_IR)) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
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if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
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get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
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return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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break;
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#endif
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}
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}
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#endif
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return 0;
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}
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static int ctr32(CPURISCVState *env, int csrno)
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{
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if (!riscv_cpu_is_32bit(env)) {
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return -RISCV_EXCP_ILLEGAL_INST;
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}
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return ctr(env, csrno);
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}
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#if !defined(CONFIG_USER_ONLY)
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static int any(CPURISCVState *env, int csrno)
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{
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return 0;
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}
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static int any32(CPURISCVState *env, int csrno)
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{
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if (!riscv_cpu_is_32bit(env)) {
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return -RISCV_EXCP_ILLEGAL_INST;
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}
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return any(env, csrno);
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}
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static int smode(CPURISCVState *env, int csrno)
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{
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return -!riscv_has_ext(env, RVS);
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@ -161,6 +182,16 @@ static int hmode(CPURISCVState *env, int csrno)
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return -RISCV_EXCP_ILLEGAL_INST;
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}
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static int hmode32(CPURISCVState *env, int csrno)
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{
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if (!riscv_cpu_is_32bit(env)) {
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return 0;
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}
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return hmode(env, csrno);
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}
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static int pmp(CPURISCVState *env, int csrno)
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{
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return -!riscv_feature(env, RISCV_FEATURE_PMP);
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@ -310,7 +341,6 @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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@ -324,7 +354,6 @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
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#endif
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return 0;
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}
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#endif /* TARGET_RISCV32 */
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#if defined(CONFIG_USER_ONLY)
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static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
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@ -333,13 +362,11 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = cpu_get_host_ticks() >> 32;
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return 0;
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}
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#endif
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#else /* CONFIG_USER_ONLY */
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@ -355,7 +382,6 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
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{
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uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
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@ -367,7 +393,6 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
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*val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
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return 0;
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}
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#endif
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/* Machine constants */
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@ -406,19 +431,17 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
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static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
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static const target_ulong vsip_writable_mask = MIP_VSSIP;
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#if defined(TARGET_RISCV32)
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static const char valid_vm_1_10[16] = {
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static const char valid_vm_1_10_32[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV32] = 1
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};
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#elif defined(TARGET_RISCV64)
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static const char valid_vm_1_10[16] = {
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static const char valid_vm_1_10_64[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV39] = 1,
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[VM_1_10_SV48] = 1,
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[VM_1_10_SV57] = 1
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};
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#endif /* CONFIG_USER_ONLY */
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/* Machine Information Registers */
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static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
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@ -441,7 +464,11 @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
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static int validate_vm(CPURISCVState *env, target_ulong vm)
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{
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return valid_vm_1_10[vm & 0xf];
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if (riscv_cpu_is_32bit(env)) {
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return valid_vm_1_10_32[vm & 0xf];
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} else {
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return valid_vm_1_10_64[vm & 0xf];
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}
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}
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static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
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@ -459,13 +486,14 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
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MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
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MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
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MSTATUS_TW;
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#if defined(TARGET_RISCV64)
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/*
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* RV32: MPV and GVA are not in mstatus. The current plan is to
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* add them to mstatush. For now, we just don't support it.
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*/
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mask |= MSTATUS_MPV | MSTATUS_GVA;
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#endif
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if (!riscv_cpu_is_32bit(env)) {
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/*
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* RV32: MPV and GVA are not in mstatus. The current plan is to
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* add them to mstatush. For now, we just don't support it.
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*/
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mask |= MSTATUS_MPV | MSTATUS_GVA;
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}
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mstatus = (mstatus & ~mask) | (val & mask);
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@ -477,7 +505,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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#ifdef TARGET_RISCV32
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static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mstatus >> 32;
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@ -497,7 +524,6 @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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#endif
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static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
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{
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@ -895,10 +921,10 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
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static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->hstatus;
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#ifdef TARGET_RISCV64
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/* We only support 64-bit VSXL */
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*val = set_field(*val, HSTATUS_VSXL, 2);
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#endif
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if (!riscv_cpu_is_32bit(env)) {
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/* We only support 64-bit VSXL */
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*val = set_field(*val, HSTATUS_VSXL, 2);
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}
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/* We only support little endian */
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*val = set_field(*val, HSTATUS_VSBE, 0);
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return 0;
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@ -907,11 +933,9 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
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static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
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{
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env->hstatus = val;
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#ifdef TARGET_RISCV64
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if (get_field(val, HSTATUS_VSXL) != 2) {
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if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
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qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
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}
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#endif
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if (get_field(val, HSTATUS_VSBE) != 0) {
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qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
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}
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@ -1053,11 +1077,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
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return -RISCV_EXCP_ILLEGAL_INST;
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}
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#if defined(TARGET_RISCV32)
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*val = env->htimedelta & 0xffffffff;
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#else
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*val = env->htimedelta;
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#endif
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return 0;
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}
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@ -1067,15 +1087,14 @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
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return -RISCV_EXCP_ILLEGAL_INST;
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}
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#if defined(TARGET_RISCV32)
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env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
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#else
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env->htimedelta = val;
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#endif
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if (riscv_cpu_is_32bit(env)) {
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env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
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} else {
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env->htimedelta = val;
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}
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
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{
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if (!env->rdtime_fn) {
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@ -1095,7 +1114,6 @@ static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
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env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
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return 0;
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}
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#endif
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/* Virtual CSR Registers */
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static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
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@ -1374,26 +1392,20 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* User Timers and Counters */
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[CSR_CYCLE] = { ctr, read_instret },
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[CSR_INSTRET] = { ctr, read_instret },
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#if defined(TARGET_RISCV32)
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[CSR_CYCLEH] = { ctr, read_instreth },
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[CSR_INSTRETH] = { ctr, read_instreth },
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#endif
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[CSR_CYCLEH] = { ctr32, read_instreth },
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[CSR_INSTRETH] = { ctr32, read_instreth },
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/* In privileged mode, the monitor will have to emulate TIME CSRs only if
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* rdtime callback is not provided by machine/platform emulation */
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[CSR_TIME] = { ctr, read_time },
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#if defined(TARGET_RISCV32)
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[CSR_TIMEH] = { ctr, read_timeh },
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#endif
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[CSR_TIMEH] = { ctr32, read_timeh },
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#if !defined(CONFIG_USER_ONLY)
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/* Machine Timers and Counters */
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[CSR_MCYCLE] = { any, read_instret },
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[CSR_MINSTRET] = { any, read_instret },
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#if defined(TARGET_RISCV32)
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[CSR_MCYCLEH] = { any, read_instreth },
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[CSR_MINSTRETH] = { any, read_instreth },
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#endif
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[CSR_MCYCLEH] = { any32, read_instreth },
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[CSR_MINSTRETH] = { any32, read_instreth },
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/* Machine Information Registers */
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[CSR_MVENDORID] = { any, read_zero },
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@ -1410,9 +1422,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
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[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
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#if defined(TARGET_RISCV32)
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[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
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#endif
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[CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
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[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
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@ -1452,9 +1462,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
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[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
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[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
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#if defined(TARGET_RISCV32)
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[CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
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#endif
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[CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
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[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
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[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
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@ -1477,9 +1485,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
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[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
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[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
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#if defined(TARGET_RISCV32)
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[CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
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[CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
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#endif
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[CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
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[CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
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#endif /* !CONFIG_USER_ONLY */
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};
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