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qemu/target/riscv
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Anup Patel 435774992e target/riscv: Update default priority table for local interrupts 
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
   and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
   (not mandatory) priority assignments.

We update the default priority table and hviprio mapping as-per above.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03 10:03:20 +10:00
..
insn_trans target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
cpu_helper.c target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
cpu_user.h
cpu-param.h Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
cpu.c target/riscv: Don't force update priv spec version to latest 2022-07-03 10:03:20 +10:00
cpu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits 2022-07-03 10:03:20 +10:00
debug.c target/riscv/debug.c: keep experimental rv128 support working 2022-06-10 09:31:42 +10:00
debug.h target/riscv: csr: Hook debug CSR read/write 2022-04-22 10:35:16 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c target/riscv: correct "code should not be reached" for x-rv128 2022-02-16 12:24:18 +10:00
helper.h target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
insn16.decode target/riscv: accessors to registers upper part and 128-bit load/store 2022-01-08 15:46:10 +10:00
insn32.decode target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
instmap.h
internals.h target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions 2022-06-10 09:31:42 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
meson.build target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
monitor.c target/riscv: Fix incorrect PTE merge in walk_pte 2022-04-29 10:47:46 +10:00
op_helper.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmp.c target/riscv/pmp: guard against PMP ranges with a negative size 2022-07-03 10:03:20 +10:00
pmp.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmu.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
pmu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
sbi_ecall_interface.h Clean up ill-advised or unusual header guards 2022-05-11 16:50:01 +02:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h
translate.c target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
vector_helper.c target/riscv: rvv: Add tail agnostic for vector permutation instructions 2022-06-10 09:31:42 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00