Peter Maydell 935fe442dc hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 ... The code for handling the NVIC SHPR1 register intends to permit byte and halfword accesses (as the architecture requires). However the 'case' line for it only lists the base address of the register, so attempts to access bytes other than the first one end up in the "bad write" default logic. This bug was added accidentally when we split out the SHPR1 logic from SHPR2 and SHPR3 to support v6M. Fixes: 7c9140afd5 ("nvic: Handle ARMv6-M SCS reserved registers") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- The Zephyr RTOS happens to access SHPR1 byte at a time, which is how I spotted this.		2019-02-15 09:56:39 +00:00
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allwinner-a10-pic.c
apic_common.c
apic.c	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
arm_gic_common.c	hw/intc/arm_gic: Drop GIC_BASE_IRQ macro	2018-09-25 15:13:24 +01:00
arm_gic_kvm.c	intc/arm_gic: Add the virtualization extensions to the GIC state	2018-08-14 17:17:20 +01:00
arm_gic.c	hw/intc/arm_gic: Drop GIC_BASE_IRQ macro	2018-09-25 15:13:24 +01:00
arm_gicv2m.c
arm_gicv3_common.c	hw/intc/arm_gicv3_common: Move gicd shift bug handling to gicv3_post_load	2018-08-06 16:19:33 +01:00
arm_gicv3_cpuif.c	target/arm: Introduce arm_hcr_el2_eff	2018-12-13 14:41:24 +00:00
arm_gicv3_dist.c	hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR	2018-06-22 13:28:34 +01:00
arm_gicv3_its_common.c
arm_gicv3_its_kvm.c	hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset	2018-08-20 11:24:31 +01:00
arm_gicv3_kvm.c	hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regions	2018-06-22 13:28:36 +01:00
arm_gicv3_redist.c	hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR	2018-06-22 13:28:34 +01:00
arm_gicv3.c	hw/intc/arm_gicv3: Introduce redist-region-count array property	2018-06-22 13:28:36 +01:00
armv7m_nvic.c	hw/intc/armv7m_nvic: Allow byte accesses to SHPR1	2019-02-15 09:56:39 +00:00
aspeed_vic.c
bcm2835_ic.c
bcm2836_control.c
etraxfs_pic.c
exynos4210_combiner.c
exynos4210_gic.c	hw/intc/exynos4210_gic: Turn instance_init into realize function	2018-07-23 15:21:27 +01:00
gic_internal.h	hw/intc/arm_gic: Drop GIC_BASE_IRQ macro	2018-09-25 15:13:24 +01:00
gicv3_internal.h
grlib_irqmp.c
heathrow_pic.c
i8259_common.c
i8259.c
imx_avic.c
imx_gpcv2.c
intc.c
ioapic_common.c	ioapic: support "info irq"	2018-06-28 19:05:37 +02:00
ioapic.c	ioapic: use TYPE_FOO MACRO than constant string	2019-01-09 11:33:47 +01:00
lm32_pic.c
Makefile.objs	spapr/xive: introduce a XIVE interrupt controller	2018-12-21 09:37:38 +11:00
mips_gic.c
nios2_iic.c
omap_intc.c
ompic.c
openpic_kvm.c
openpic.c
pl190.c
puv3_intc.c	intc/puv3_intc: Convert sysbus init function to realize function	2018-12-13 13:47:59 +00:00
realview_gic.c	hw/*/realview: Fix introspection problem with 'realview_mpcore' & 'realview_gic'	2018-07-17 13:12:49 +01:00
s390_flic_kvm.c	vmstate: constify VMStateField	2018-11-27 15:35:15 +01:00
s390_flic.c
sh_intc.c
slavio_intctl.c
spapr_xive.c	spapr: move the interrupt presenters under machine_data	2019-02-04 18:44:18 +11:00
trace-events	nvic: Expose NMI line	2018-08-20 11:24:33 +01:00
vgic_common.h
xics_kvm.c	ppc: Move spapr-related prototypes from xics.h into a seperate header file	2019-01-22 05:14:33 +01:00
xics_pnv.c	ppc/xics: introduce ICP DeviceRealize and DeviceReset handlers	2018-07-03 09:56:51 +10:00
xics_spapr.c	spapr: move the interrupt presenters under machine_data	2019-02-04 18:44:18 +11:00
xics.c	spapr: move the qemu_irq array under the machine	2019-01-09 09:28:14 +11:00
xilinx_intc.c
xive.c	xive: add a get_tctx() method to the XiveRouter	2019-02-04 18:44:18 +11:00
xlnx-pmu-iomod-intc.c
xlnx-zynqmp-ipi.c