qemu/target/loongarch/insn_trans
Richard Henderson c2b618a8c1 target/loongarch: Disassemble jirl properly
While jirl shares the same instruction format as bne etc,
it is not assembled the same.  In particular, rd is printed
first not second and the immediate is not pc-relative.

Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-23 15:36:36 -10:00
..
trans_arith.c.inc
trans_atomic.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_bit.c.inc target/loongarch: bstrins.w src register need EXT_NONE 2022-10-17 10:28:35 +08:00
trans_branch.c.inc target/loongarch: Disassemble jirl properly 2023-01-23 15:36:36 -10:00
trans_extra.c.inc target/loongarch: Add timer related instructions support. 2022-06-06 18:09:03 +00:00
trans_farith.c.inc target/loongarch: Fix return value of CHECK_FPE 2022-11-07 10:54:11 +08:00
trans_fcmp.c.inc target/loongarch: Fix emulation of float-point disable exception 2022-11-04 17:10:53 +08:00
trans_fcnv.c.inc target/loongarch: Add floating point conversion instruction translation 2022-06-06 18:09:03 +00:00
trans_fmemory.c.inc target/loongarch: Fix emulation of float-point disable exception 2022-11-04 17:10:53 +08:00
trans_fmov.c.inc target/loongarch: Fix emulation of float-point disable exception 2022-11-04 17:10:53 +08:00
trans_memory.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_privileged.c.inc target/loongarch: Separate the hardware flags into MMU index and PLV 2022-11-07 10:54:08 +08:00
trans_shift.c.inc target/loongarch: Add fixed point shift instruction translation 2022-06-06 18:09:03 +00:00