qemu/include/hw/riscv
Alistair Francis 099be0358e hw/riscv: sifive_u: Allow specifying the CPU
Allow the user to specify the main application CPU for the sifive_u
machine.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
..
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
boot.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: Hook GPIO controllers 2020-09-09 15:54:19 -07:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h sifive_e: Rename memmap enum constants 2020-09-18 13:49:48 -04:00
sifive_u.h hw/riscv: sifive_u: Allow specifying the CPU 2020-10-22 12:00:22 -07:00
spike.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
virt.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00