qemu/target/i386
Paolo Bonzini a290e43f58 target/i386: pcrel: store low bits of physical address in data[0]
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with.  Because a TB will not span two pages, QEMU
stores all the low bits of EIP in the instruction data and replaces them
in x86_restore_state_to_opc.  Bits 12 and higher (which may vary between
executions of a PCREL TB, since these only use the physical address in
the hash key) are kept unmodified from env->eip.  The assumption is that
these bits of EIP, unlike bits 0-11, will not change as the translation
block executes.

Unfortunately, this is incorrect when the CS base is not aligned to a page.
Then the linear address of the instructions (i.e. the one with the
CS base addred) indeed will never span two pages, but bits 12+ of EIP
can actually change.  For example, if CS base is 0x80262200 and EIP =
0x6FF4, the first instruction in the translation block will be at linear
address 0x802691F4.  Even a very small TB will cross to EIP = 0x7xxx,
while the linear addresses will remain comfortably within a single page.

The fix is simply to use the low bits of the linear address for data[0],
since those don't change.  Then x86_restore_state_to_opc uses tb->cs_base
to compute a temporary linear address (referring to some unknown
instruction in the TB, but with the correct values of bits 12 and higher);
the low bits are replaced with data[0], and EIP is obtained by subtracting
again the CS base.

Huge thanks to Mark Cave-Ayland for the image and initial debugging,
and to Gitlab user @kjliew for help with bisecting another occurrence
of (hopefully!) the same bug.

It should be relatively easy to write a testcase that performs MMIO on
an EIP with different bits 12+ than the first instruction of the translation
block; any help is welcome.

Fixes: e3a79e0e87 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11)
Cc: qemu-stable@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 729ba8e933)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: fixup in target/i386/tcg/tcg-cpu.c target/i386/tcg/translate.c for
 v7.2.0-1839-g2e3afe8e19 "target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`")
2024-01-20 17:41:47 +03:00
..
hax Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
hvf hvf: Enable RDTSCP support 2022-07-13 00:05:39 +02:00
kvm kvm: Introduce kvm_arch_get_default_type hook 2023-09-11 10:53:50 +03:00
nvmm Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
tcg target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 17:41:47 +03:00
whpx Drop useless casts from g_malloc() & friends to pointer 2022-10-22 23:15:40 +02:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
arch_memory_mapping.c
cpu-dump.c monitor: Trim some trailing space from human-readable output 2021-10-31 21:05:40 +01:00
cpu-internal.h i386: split off sysemu part of cpu.c 2021-05-10 15:41:52 -04:00
cpu-param.h target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX 2022-10-18 13:58:04 +02:00
cpu-qom.h target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro 2022-03-06 22:23:09 +01:00
cpu-sysemu.c Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
cpu.c target/i386: Change wrong XFRM value in SGX CPUID leaf 2023-04-27 08:53:10 +03:00
cpu.h target/i386: Fix 32-bit wrapping of pc/eip computation 2024-01-20 17:41:47 +03:00
gdbstub.c target/i386: fix byte swap issue with XMM register access 2022-04-20 16:04:20 +01:00
helper.c target/i386: Use cpu_unwind_state_data for tpr access 2022-11-01 08:31:37 +11:00
helper.h target/i386: Expand eflags updates inline 2022-11-01 08:31:41 +11:00
host-cpu.c i386: do not call cpudef-only models functions for max, host, base 2021-07-23 15:47:13 +02:00
host-cpu.h accel-cpu: make cpu_realizefn return a bool 2021-05-10 15:41:50 -04:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
machine.c i386: kvm: extend kvm_{get, put}_vcpu_events to support pending triple fault 2022-10-10 09:23:16 +02:00
meson.build target/i386/sev: Remove stubs by using code elision 2021-10-13 10:47:49 +02:00
monitor.c monitor: remove 'info ioapic' HMP command 2021-11-02 15:55:13 +00:00
ops_sse_header.h target/i386: implement FMA instructions 2022-10-22 09:05:54 +02:00
ops_sse.h target/i386: fix avx2 instructions vzeroall and vpermdq 2023-05-18 21:10:00 +03:00
sev-sysemu-stub.c monitor: Reduce hmp_info_sev() declaration 2021-10-13 10:47:49 +02:00
sev.c qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities 2022-04-06 10:50:37 +02:00
sev.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
shift_helper_template.h
svm.h target/i386: Added vVMLOAD and vVMSAVE feature 2021-09-13 13:56:26 +02:00
trace-events * Update the references to some doc files (use *.rst instead of *.txt) 2021-06-02 17:08:11 +01:00
trace.h
xsave_helper.c x86: add support for KVM_CAP_XSAVE2 and AMX state migration 2022-03-15 11:50:50 +01:00