accel-cpu: make cpu_realizefn return a bool
overall, all devices' realize functions take an Error **errp, but return void. hw/core/qdev.c code, which realizes devices, therefore does: local_err = NULL; dc->realize(dev, &local_err); if (local_err != NULL) { goto fail; } However, we can improve at least accel_cpu to return a meaningful bool value. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210322132800.7470-9-cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -98,14 +98,14 @@ void accel_cpu_instance_init(CPUState *cpu)
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}
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}
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void accel_cpu_realizefn(CPUState *cpu, Error **errp)
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bool accel_cpu_realizefn(CPUState *cpu, Error **errp)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) {
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/* NB: errp parameter is unused currently */
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cc->accel_cpu->cpu_realizefn(cpu, errp);
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return cc->accel_cpu->cpu_realizefn(cpu, errp);
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}
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return true;
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}
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static const TypeInfo accel_cpu_type = {
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5
cpu.c
5
cpu.c
@ -130,8 +130,9 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cpu_list_add(cpu);
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accel_cpu_realizefn(cpu, errp);
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if (!accel_cpu_realizefn(cpu, errp)) {
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return;
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}
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#ifdef CONFIG_TCG
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/* NB: errp parameter is unused currently */
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if (tcg_enabled()) {
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@ -32,7 +32,7 @@ typedef struct AccelCPUClass {
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void (*cpu_class_init)(CPUClass *cc);
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void (*cpu_instance_init)(CPUState *cpu);
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void (*cpu_realizefn)(CPUState *cpu, Error **errp);
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bool (*cpu_realizefn)(CPUState *cpu, Error **errp);
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} AccelCPUClass;
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#endif /* ACCEL_CPU_H */
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@ -89,6 +89,6 @@ void accel_cpu_instance_init(CPUState *cpu);
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* @cpu: The CPU that needs to call accel-specific cpu realization.
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* @errp: currently unused.
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*/
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void accel_cpu_realizefn(CPUState *cpu, Error **errp);
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bool accel_cpu_realizefn(CPUState *cpu, Error **errp);
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#endif /* QEMU_ACCEL_H */
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@ -80,7 +80,7 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu)
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return phys_bits;
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}
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void host_cpu_realizefn(CPUState *cs, Error **errp)
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bool host_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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@ -97,10 +97,11 @@ void host_cpu_realizefn(CPUState *cs, Error **errp)
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error_setg(errp, "phys-bits should be between 32 and %u "
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" (but is %u)",
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TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
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return;
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return false;
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}
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cpu->phys_bits = phys_bits;
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}
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return true;
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}
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#define CPUID_MODEL_ID_SZ 48
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@ -12,7 +12,7 @@
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void host_cpu_instance_init(X86CPU *cpu);
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void host_cpu_max_instance_init(X86CPU *cpu);
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void host_cpu_realizefn(CPUState *cs, Error **errp);
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bool host_cpu_realizefn(CPUState *cs, Error **errp);
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void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);
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@ -18,7 +18,7 @@
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#include "kvm_i386.h"
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#include "hw/core/accel-cpu.h"
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static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
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static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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@ -41,7 +41,7 @@ static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
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MSR_IA32_UCODE_REV);
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}
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}
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host_cpu_realizefn(cs, errp);
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return host_cpu_realizefn(cs, errp);
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}
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/*
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@ -96,7 +96,7 @@ static void x86_cpu_machine_done(Notifier *n, void *unused)
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}
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}
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static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
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static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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@ -132,12 +132,14 @@ static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
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/* ... SMRAM with higher priority, linked from /machine/smram. */
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cpu->machine_done.notify = x86_cpu_machine_done;
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qemu_add_machine_init_done_notifier(&cpu->machine_done);
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return true;
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}
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#else /* CONFIG_USER_ONLY */
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static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
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static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
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{
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return true;
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}
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#endif /* !CONFIG_USER_ONLY */
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