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Richard Henderson 9eb4f58918 target/arm: Set MVFR0.FPSP for ARMv5 cpus 
We are going to convert FEATURE tests to ISAR tests,
so FPSP needs to be set for these cpus, like we have
already for FPDP.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214181547.21408-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-21 16:07:03 +00:00
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alpha
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arm
target/arm: Set MVFR0.FPSP for ARMv5 cpus
2020-02-21 16:07:03 +00:00
cris
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
hppa
target/hppa: Allow, but diagnose, LDCW aligned only mod 4
2020-01-27 10:49:51 -08:00
i386
target/i386/whpx: Remove superfluous semicolon
2020-02-18 20:20:49 +01:00
lm32
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
m68k
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
microblaze
qdev: set properties with device_class_set_props()
2020-01-24 20:59:15 +01:00
mips
target/mips: Separate FPU-related helpers into their own file
2020-02-04 08:53:54 +01:00
moxie
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
nios2
qdev: set properties with device_class_set_props()
2020-01-24 20:59:15 +01:00
openrisc
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
ppc
target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition
2020-02-21 09:15:04 +11:00
riscv
riscv: Separate FPU register size from core register size in gdbstub [v2]
2020-02-10 12:01:36 -08:00
s390x
s390x: sigp: Fix sense running reporting
2020-01-27 12:13:10 +01:00
sh4
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
sparc
qdev: set properties with device_class_set_props()
2020-01-24 20:59:15 +01:00
tilegx
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
tricore
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00
unicore32
…
xtensa
cpu: Use cpu_class_set_parent_reset()
2020-01-24 20:59:06 +01:00