
The timer memory range begins at 0x10f0, so that address 0x1120 shows up as 0x30, 0x1130 shows up as 0x40, etc. However, the address decoding (other than TFRR) is not adjusted for this, causing the wrong registers to be accessed. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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Read the documentation in qemu-doc.html or on http://wiki.qemu.org - QEMU team
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