Eduardo Habkost 8110fa1d94 Use DECLARE_*CHECKER* macros ... Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>		2020-09-09 09:27:09 -04:00
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boot_opensbi.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
boot.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
riscv_hart.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
riscv_htif.h
sifive_clint.h	hw/riscv: Allow creating multiple instances of CLINT	2020-08-25 09:11:35 -07:00
sifive_cpu.h
sifive_e_prci.h
sifive_e.h
sifive_gpio.h	hw/riscv: sifive_gpio: Add a new 'ngpio' property	2020-06-19 08:24:07 -07:00
sifive_plic.h	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_test.h
sifive_u_otp.h
sifive_u_prci.h
sifive_u.h	hw/riscv: sifive_u: Add a dummy L2 cache controller device	2020-08-21 22:37:55 -07:00
sifive_uart.h
spike.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
virt.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00