c0d964076c
Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
92 lines
4.1 KiB
C
92 lines
4.1 KiB
C
#ifndef TARGET_PPC_CPU_INIT_H
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#define TARGET_PPC_CPU_INIT_H
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#define PPC_INSNS_FLAGS_POWER9 \
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(PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \
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PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | \
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PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
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PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \
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PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \
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PPC_CILDST)
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#define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9
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#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10
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#define PPC_INSNS_FLAGS2_POWER_COMMON \
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(PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
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PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \
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PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \
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PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
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PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
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#define PPC_INSNS_FLAGS2_POWER9 \
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(PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM)
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#define PPC_INSNS_FLAGS2_POWER10 \
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(PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310)
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#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10
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#define PPC_MSR_MASK_POWER_COMMON \
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((1ull << MSR_SF) | \
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(1ull << MSR_HV) | \
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(1ull << MSR_VR) | \
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(1ull << MSR_VSX) | \
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(1ull << MSR_EE) | \
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(1ull << MSR_PR) | \
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(1ull << MSR_FP) | \
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(1ull << MSR_ME) | \
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(1ull << MSR_FE0) | \
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(1ull << MSR_SE) | \
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(1ull << MSR_DE) | \
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(1ull << MSR_FE1) | \
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(1ull << MSR_IR) | \
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(1ull << MSR_DR) | \
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(1ull << MSR_PMM) | \
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(1ull << MSR_RI) | \
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(1ull << MSR_LE))
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#define PPC_MSR_MASK_POWER9 \
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(PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM))
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#define PPC_MSR_MASK_POWER10 \
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PPC_MSR_MASK_POWER_COMMON
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#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10
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#define PPC_PCR_MASK_POWER9 \
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(PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07)
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#define PPC_PCR_MASK_POWER10 \
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(PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00)
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#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10
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#define PPC_PCR_SUPPORTED_POWER9 \
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(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05)
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#define PPC_PCR_SUPPORTED_POWER10 \
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(PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10)
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#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10
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#define PPC_LPCR_MASK_POWER9 \
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(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \
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(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | \
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LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | \
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(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | \
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LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | \
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LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE)
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/* DD2 adds an extra HAIL bit */
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#define PPC_LPCR_MASK_POWER10 \
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(PPC_LPCR_MASK_POWER9 | LPCR_HAIL)
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#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10
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#define POWERPC_FLAGS_POWER_COMMON \
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(POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
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POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \
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POWERPC_FLAG_VSX | POWERPC_FLAG_SCV)
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#define POWERPC_FLAGS_POWER9 \
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(POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM)
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#define POWERPC_FLAGS_POWER10 \
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(POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB)
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#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10
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#endif /* TARGET_PPC_CPU_INIT_H */
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