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target/ppc: Add Power11 DD2.0 processor

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Add CPU target code to add support for new Power11 Processor.

Power11 core is same as Power10, hence reuse functions defined for
Power10.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Aditya Gupta 2024-07-31 11:20:21 +05:30 committed by Nicholas Piggin
parent ac0fbbb2d0
commit c0d964076c
7 changed files with 86 additions and 0 deletions
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7
target/ppc/compat.c
View File

@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
.pcr_level = PCR_COMPAT_3_10,
.max_vthreads = 8,
},
{ /* POWER11, ISA3.10 */
.name = "power11",
.pvr = CPU_POWERPC_LOGICAL_3_10_P11,
.pcr = PCR_COMPAT_3_10,
.pcr_level = PCR_COMPAT_3_10,
.max_vthreads = 8,
},
};
static const CompatInfo *compat_by_pvr(uint32_t pvr)

3
target/ppc/cpu-models.c
View File

@ -734,6 +734,8 @@
"POWER9 v2.2")
POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
"POWER10 v2.0")
POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER11,
"POWER11_v2.0")
#endif /* defined (TARGET_PPC64) */
/***************************************************************************/
@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "power8nvl", "power8nvl_v1.0" },
{ "power9", "power9_v2.2" },
{ "power10", "power10_v2.0" },
{ "power11", "power11_v2.0" },
#endif
/* Generic PowerPCs */

3
target/ppc/cpu-models.h
View File

@ -354,6 +354,8 @@ enum {
CPU_POWERPC_POWER10_BASE = 0x00800000,
CPU_POWERPC_POWER10_DD1 = 0x00801100,
CPU_POWERPC_POWER10_DD20 = 0x00801200,
CPU_POWERPC_POWER11_BASE = 0x00820000,
CPU_POWERPC_POWER11_DD20 = 0x00821200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
@ -391,6 +393,7 @@ enum {
CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
CPU_POWERPC_LOGICAL_3_10_P11 = 0x0F000007,
};
/* System version register (used on MPC 8xxx) */

2
target/ppc/cpu.h
View File

@ -216,6 +216,8 @@ typedef enum powerpc_excp_t {
POWERPC_EXCP_POWER9,
/* POWER10 exception model */
POWERPC_EXCP_POWER10,
/* POWER11 exception model */
POWERPC_EXCP_POWER11,
} powerpc_excp_t;
/*****************************************************************************/

60
target/ppc/cpu_init.c
View File

@ -6675,6 +6675,66 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
}
static void init_proc_POWER11(CPUPPCState *env)
{
init_proc_POWER10(env);
}
static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
{
uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
return true;
}
if (base != pcc_base) {
return false;
}
if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
return true;
}
return false;
}
POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->fw_name = "PowerPC,POWER11";
dc->desc = "POWER11";
pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11;
pcc->pvr_match = ppc_pvr_match_power11;
pcc->pcr_mask = PPC_PCR_MASK_POWER11;
pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11;
pcc->init_proc = init_proc_POWER11;
pcc->check_pow = check_pow_nocheck;
pcc->check_attn = check_attn_hid0_power9;
pcc->insns_flags = PPC_INSNS_FLAGS_POWER11;
pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11;
pcc->msr_mask = PPC_MSR_MASK_POWER11;
pcc->lpcr_mask = PPC_LPCR_MASK_POWER11;
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
#if !defined(CONFIG_USER_ONLY)
/* segment page size remain the same */
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
pcc->radix_page_info = &POWER10_radix_page_info;
pcc->lrg_decr_bits = 56;
#endif
pcc->excp_model = POWERPC_EXCP_POWER11;
pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
pcc->bfd_mach = bfd_mach_ppc64;
pcc->flags = POWERPC_FLAGS_POWER11;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
}
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
{

7
target/ppc/cpu_init.h
View File

@ -12,6 +12,7 @@
PPC_CILDST)
#define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9
#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10
#define PPC_INSNS_FLAGS2_POWER_COMMON \
(PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \
@ -25,6 +26,7 @@
(PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM)
#define PPC_INSNS_FLAGS2_POWER10 \
(PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310)
#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10
#define PPC_MSR_MASK_POWER_COMMON \
((1ull << MSR_SF) | \
@ -49,16 +51,19 @@
(PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM))
#define PPC_MSR_MASK_POWER10 \
PPC_MSR_MASK_POWER_COMMON
#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10
#define PPC_PCR_MASK_POWER9 \
(PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07)
#define PPC_PCR_MASK_POWER10 \
(PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00)
#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10
#define PPC_PCR_SUPPORTED_POWER9 \
(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05)
#define PPC_PCR_SUPPORTED_POWER10 \
(PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10)
#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10
#define PPC_LPCR_MASK_POWER9 \
(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \
@ -70,6 +75,7 @@
/* DD2 adds an extra HAIL bit */
#define PPC_LPCR_MASK_POWER10 \
(PPC_LPCR_MASK_POWER9 | LPCR_HAIL)
#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10
#define POWERPC_FLAGS_POWER_COMMON \
(POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
@ -80,5 +86,6 @@
(POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM)
#define POWERPC_FLAGS_POWER10 \
(POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB)
#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10
#endif /* TARGET_PPC_CPU_INIT_H */

4
target/ppc/excp_helper.c
View File

@ -1661,6 +1661,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_POWER8:
case POWERPC_EXCP_POWER9:
case POWERPC_EXCP_POWER10:
case POWERPC_EXCP_POWER11:
powerpc_excp_books(cpu, excp);
break;
default:
@ -2018,6 +2019,7 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
return p8_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER9:
case POWERPC_EXCP_POWER10:
case POWERPC_EXCP_POWER11:
return p9_next_unmasked_interrupt(env);
default:
break;
@ -2378,6 +2380,7 @@ static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
return p8_deliver_interrupt(env, interrupt);
case POWERPC_EXCP_POWER9:
case POWERPC_EXCP_POWER10:
case POWERPC_EXCP_POWER11:
return p9_deliver_interrupt(env, interrupt);
default:
break;
@ -3168,6 +3171,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
case POWERPC_EXCP_POWER8:
case POWERPC_EXCP_POWER9:
case POWERPC_EXCP_POWER10:
case POWERPC_EXCP_POWER11:
/*
* Machine check codes can be found in processor User Manual or
* Linux or skiboot source.