ead5078cf1
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V
bit due to an ITLB interruption in the middle of a series of ds/addc
instructions (from the divU milicode library) generated the wrong division
result and thus triggered a Linux kernel crash.
Link: https://lore.kernel.org/lkml/718b8afe-222f-4b3a-96d3-93af0e4ceff1@roeck-us.net/
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Fixes: 931adff314 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64")
Cc: qemu-stable@nongnu.org # v8.2+
214 lines
7.3 KiB
C
214 lines
7.3 KiB
C
/*
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* HPPA emulation cpu helpers for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "fpu/softfloat.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/qemu-print.h"
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target_ulong cpu_hppa_get_psw(CPUHPPAState *env)
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{
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target_ulong psw;
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target_ulong mask1 = (target_ulong)-1 / 0xf;
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target_ulong maskf = (target_ulong)-1 / 0xffff * 0xf;
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/* Fold carry bits down to 8 consecutive bits. */
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/* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */
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psw = (env->psw_cb >> 4) & mask1;
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/* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */
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psw |= psw >> 3;
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/* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */
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psw |= psw >> 6;
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psw &= maskf;
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/* .............bcd............efgh............ijkl............mnop */
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psw |= psw >> 12;
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/* .............bcd.........bcdefgh........efghijkl........ijklmnop */
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psw |= env->psw_cb_msb << 39;
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/* .............bcd........abcdefgh........efghijkl........ijklmnop */
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/* For hppa64, the two 8-bit fields are discontiguous. */
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if (hppa_is_pa20(env)) {
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psw = (psw & 0xff00000000ull) | ((psw & 0xff) << 8);
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} else {
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psw = (psw & 0xff) << 8;
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}
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psw |= env->psw_n * PSW_N;
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psw |= ((env->psw_v >> 31) & 1) * PSW_V;
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psw |= env->psw | env->psw_xb;
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return psw;
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}
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void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw)
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{
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uint64_t reserved;
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target_ulong cb = 0;
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/* Do not allow reserved bits to be set. */
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if (hppa_is_pa20(env)) {
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reserved = MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4);
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reserved |= PSW_G; /* PA1.x only */
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reserved |= PSW_E; /* not implemented */
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} else {
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reserved = MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2);
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reserved |= PSW_O | PSW_W; /* PA2.0 only */
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reserved |= PSW_E | PSW_Y | PSW_Z; /* not implemented */
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}
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psw &= ~reserved;
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env->psw = psw & (uint32_t)~(PSW_B | PSW_N | PSW_V | PSW_X | PSW_CB);
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env->psw_xb = psw & (PSW_X | PSW_B);
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env->psw_n = (psw / PSW_N) & 1;
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env->psw_v = -((psw / PSW_V) & 1);
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env->psw_cb_msb = (psw >> 39) & 1;
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cb |= ((psw >> 38) & 1) << 60;
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cb |= ((psw >> 37) & 1) << 56;
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cb |= ((psw >> 36) & 1) << 52;
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cb |= ((psw >> 35) & 1) << 48;
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cb |= ((psw >> 34) & 1) << 44;
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cb |= ((psw >> 33) & 1) << 40;
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cb |= ((psw >> 32) & 1) << 36;
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cb |= ((psw >> 15) & 1) << 32;
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cb |= ((psw >> 14) & 1) << 28;
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cb |= ((psw >> 13) & 1) << 24;
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cb |= ((psw >> 12) & 1) << 20;
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cb |= ((psw >> 11) & 1) << 16;
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cb |= ((psw >> 10) & 1) << 12;
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cb |= ((psw >> 9) & 1) << 8;
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cb |= ((psw >> 8) & 1) << 4;
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env->psw_cb = cb;
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}
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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#ifndef CONFIG_USER_ONLY
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static const char cr_name[32][5] = {
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"RC", "CR1", "CR2", "CR3",
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"CR4", "CR5", "CR6", "CR7",
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"PID1", "PID2", "CCR", "SAR",
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"PID3", "PID4", "IVA", "EIEM",
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"ITMR", "ISQF", "IOQF", "IIR",
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"ISR", "IOR", "IPSW", "EIRR",
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"TR0", "TR1", "TR2", "TR3",
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"TR4", "TR5", "TR6", "TR7",
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};
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#endif
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CPUHPPAState *env = cpu_env(cs);
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target_ulong psw = cpu_hppa_get_psw(env);
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target_ulong psw_cb;
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char psw_c[20];
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int i, w;
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uint64_t m;
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if (hppa_is_pa20(env)) {
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w = 16;
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m = UINT64_MAX;
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} else {
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w = 8;
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m = UINT32_MAX;
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}
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qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n"
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"IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n",
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env->iasq_f >> 32, w, m & env->iaoq_f,
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hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f),
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env->iasq_b >> 32, w, m & env->iaoq_b,
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hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b));
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psw_c[0] = (psw & PSW_W ? 'W' : '-');
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psw_c[1] = (psw & PSW_E ? 'E' : '-');
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psw_c[2] = (psw & PSW_S ? 'S' : '-');
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psw_c[3] = (psw & PSW_T ? 'T' : '-');
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psw_c[4] = (psw & PSW_H ? 'H' : '-');
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psw_c[5] = (psw & PSW_L ? 'L' : '-');
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psw_c[6] = (psw & PSW_N ? 'N' : '-');
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psw_c[7] = (psw & PSW_X ? 'X' : '-');
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psw_c[8] = (psw & PSW_B ? 'B' : '-');
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psw_c[9] = (psw & PSW_C ? 'C' : '-');
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psw_c[10] = (psw & PSW_V ? 'V' : '-');
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psw_c[11] = (psw & PSW_M ? 'M' : '-');
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psw_c[12] = (psw & PSW_F ? 'F' : '-');
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psw_c[13] = (psw & PSW_R ? 'R' : '-');
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psw_c[14] = (psw & PSW_Q ? 'Q' : '-');
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psw_c[15] = (psw & PSW_P ? 'P' : '-');
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psw_c[16] = (psw & PSW_D ? 'D' : '-');
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psw_c[17] = (psw & PSW_I ? 'I' : '-');
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psw_c[18] = '\0';
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psw_cb = ((env->psw_cb >> 4) & 0x1111111111111111ull)
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| (env->psw_cb_msb << 60);
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qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n",
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w, m & psw, w, m & psw_cb, psw_c);
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c",
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i, w, m & env->gr[i],
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(i & 3) == 3 ? '\n' : ' ');
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}
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, "%-4s %0*" PRIx64 "%c",
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cr_name[i], w, m & env->cr[i],
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(i & 3) == 3 ? '\n' : ' ');
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}
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qemu_fprintf(f, "ISQB %0*" PRIx64 " IOQB %0*" PRIx64 "\n",
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w, m & env->cr_back[0], w, m & env->cr_back[1]);
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for (i = 0; i < 8; i++) {
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qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32),
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(i & 3) == 3 ? '\n' : ' ');
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}
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#endif
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if (flags & CPU_DUMP_FPU) {
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static const char rm[4][4] = { "RN", "RZ", "R+", "R-" };
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char flg[6], ena[6];
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uint32_t fpsr = env->fr0_shadow;
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flg[0] = (fpsr & R_FPSR_FLG_V_MASK ? 'V' : '-');
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flg[1] = (fpsr & R_FPSR_FLG_Z_MASK ? 'Z' : '-');
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flg[2] = (fpsr & R_FPSR_FLG_O_MASK ? 'O' : '-');
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flg[3] = (fpsr & R_FPSR_FLG_U_MASK ? 'U' : '-');
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flg[4] = (fpsr & R_FPSR_FLG_I_MASK ? 'I' : '-');
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flg[5] = '\0';
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ena[0] = (fpsr & R_FPSR_ENA_V_MASK ? 'V' : '-');
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ena[1] = (fpsr & R_FPSR_ENA_Z_MASK ? 'Z' : '-');
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ena[2] = (fpsr & R_FPSR_ENA_O_MASK ? 'O' : '-');
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ena[3] = (fpsr & R_FPSR_ENA_U_MASK ? 'U' : '-');
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ena[4] = (fpsr & R_FPSR_ENA_I_MASK ? 'I' : '-');
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ena[5] = '\0';
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qemu_fprintf(f, "FPSR %08x flag %s enable %s %s\n",
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fpsr, flg, ena, rm[FIELD_EX32(fpsr, FPSR, RM)]);
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, "FR%02d %016" PRIx64 "%c",
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i, env->fr[i], (i & 3) == 3 ? '\n' : ' ');
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}
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}
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qemu_fprintf(f, "\n");
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}
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