Commit Graph

305 Commits

Author SHA1 Message Date
Richard Henderson
f52879b441 target-sparc: Use DisasCompare and movcond in MOVCC
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
7e480893cc target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCC
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
3a49e7598b target-sparc: Use DisasCompare in Tcc
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
416fcaea1e target-sparc: Introduce DisasCompare and functions to generate it
For the moment gen_cond et al retain their existing interface,
using setcond to turn a (potential) comparison back into a boolean.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
2e655fe768 target-sparc: Tidy gen_generic_branch interface
The arguments passed are always the same.
Pass down just DisasContext instead.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
934da7ee08 target-sparc: Tidy save_npc interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
13a6dd0043 target-sparc: Tidy gen_mov_pc_npc interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
66442b07ae target-sparc: Tidy save_state interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
5b12f1e8a1 target-sparc: Tidy gen_trap_ifnofpu interface
We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
dee8913cbf target-sparc: Tidy flush_cond interface
We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
d4a288ef9c target-sparc: Tidy do_branch interfaces
We always pass cpu_cond to the r_cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:29 +00:00
Richard Henderson
fdefe51c28 Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-27 21:38:50 +02:00
Artyom Tarasenko
22036a49dd Implement address masking for SPARC v9 CPUs
According to UltraSPARC - IIi User's manual:

14.1.11 Address Masking (Impdep #125)
When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
transmit zero in the high-order 32-bits of the PC to their specified
destination registers.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-05-12 09:46:00 +00:00
Blue Swirl
0184e266cb Sparc: avoid AREG0 wrappers for memory access helpers
Adjust generation of load and store templates so that the functions
take a parameter for CPUState instead of relying on global env.

Remove wrappers. Move remaining memory helpers to ldst_helper.c.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:22:02 +00:00
Blue Swirl
fe8d8f0f1c Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:22:00 +00:00
Andreas Färber
c5f9864e89 target-sparc: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc]
  sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Fabien Chouteau
96d922a654 Improve "ta 0" shutdown
This patch replace the previous implementation with this simplified and
more complete version (no shutdown when psret == 1).

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19 11:22:57 +00:00
Richard Henderson
50c796f9d8 target-sparc: Implement FALIGNDATA inline.
This is a relatively simple sequence of shifts.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
793a137a41 target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
add545ab11 target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not
implemeneted at all.  However, this is a very simple operation
so we're better off doing this inline.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
6c07355325 target-sparc: Implement EDGE* instructions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
2dedf31497 target-sparc: Implement fpack{16,32,fix}.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:17 -07:00
Richard Henderson
f888300b81 target-sparc: Implement PDIST.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:58:48 -07:00
Richard Henderson
445167723d target-sparc: Do exceptions management fully inside the helpers.
This reduces the size of the individual translation blocks, since
we only emit a single call for each FOP rather than three.  In
addition, clear_float_exceptions expands inline to a single byte store.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:57:06 -07:00
Richard Henderson
30038fd818 target-sparc: Change fpr representation to doubles.
This allows a more efficient representation for 64-bit hosts.
It should be about the same for 32-bit hosts, as we can still
access the individual pieces of the double.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
45c7b743cd target-sparc: Undo cpu_fpr rename.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
ac11f7767f target-sparc: Extract float128 move to a function.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
61f17f6eba target-sparc: Extract common code for floating-point operations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:24 -07:00
Richard Henderson
f027c3b192 target-sparc: Make FPU/VIS helpers const when possible.
This also removes the unused ENV parameter from these helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
03fb8cfc63 target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
96eda02412 target-sparc: Add accessors for double-precision fpr access.
Begin using i64 quantities to manipulate double-precision values.
On a 64-bit host this will, for the moment, generate less efficient
code; on a 32-bit host code quality should be largely unchanged.
Code quality for 64-bit will be adjusted with a subsequent patch.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
141ae5c13f target-sparc: Mark fprs dirty in store accessor.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
208ae65722 target-sparc: Add accessors for single-precision fpr access.
Load, store, and "create destination".  This version attempts to
change the behaviour of the translator as little as possible.  We
previously used cpu_tmp32 as the temporary destination, and we
continue to use that.  This will eventually allow a change in
representation of the fprs.

Change the name of the cpu_fpr array to make certain that all
instances are converted.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:42 -07:00
Blue Swirl
7a5e4488cd Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:52 +00:00
Blue Swirl
7922703623 Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int{32,64}_helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:09 +00:00
Blue Swirl
063c367558 Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Remove wrapper functions.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:04 +00:00
Stefan Weil
f37e2a6bb3 target-sparc: Fix order of function parameters
The MinGW-w64 gcc complains about wrong parameters for
gen_helper_fpadd16_s and three other functions.

gen_helper_fpadd16_s is declared like this (hidden in lots of macros):

static inline void
 gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,
                     TCGv_i32 arg2, TCGv_i32 arg3);

So it looks like cpu_env should be the 2nd parameter.

Please review this patch as I have no environment to test it
(maybe the 1st parameter should be cpu_dst?).

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-25 19:30:00 +00:00
Blue Swirl
2ffd9176b1 Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:37 +00:00
Blue Swirl
2e2f4ade86 Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:13 +00:00
Blue Swirl
bc2653195a Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:08:22 +00:00
Artyom Tarasenko
548f66db33 Fix handling of conditional branches in delay slot of a conditional branch
Check whether dc->npc is dynamic before using its value for branch.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-06 15:08:31 +00:00
Tsuneo Saito
638737ad03 SPARC64: implement %fprs dirty bits
Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 08:26:45 +00:00
Tsuneo Saito
ccb57e0ea7 SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destination
registers.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 08:26:45 +00:00
Tsuneo Saito
b7d69dc233 SPARC64: add missing break on fmovdcc
"break" is missing on V9 fmovdcc (%icc).

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 20:44:50 +00:00
Tsuneo Saito
afcb737512 SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions
(fcmp*<16|32>) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 20:44:23 +00:00
Blue Swirl
f838e2c535 Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to check
for FPU enable state and 32 bit address masking on Sparc64.

Fix by using TB flags instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 17:30:43 +00:00
Tsuneo Saito
5f06b54718 SPARC64: fp_disabled checks on stfa/stdfa/stqfa
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:36:15 +00:00
Tsuneo Saito
e1ef36c4a3 SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:36:10 +00:00
Tsuneo Saito
8872eb4f56 SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:35:01 +00:00
Artyom Tarasenko
8e91ed3080 fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx
udivx and sdvix don't modify condition flags, so they shall not
overwrite cpu_cc_*

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 21:28:00 +00:00