Commit Graph

79 Commits

Author SHA1 Message Date
Richard Henderson
25c4d9cc84 tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:24 +00:00
Blue Swirl
614f104dfd Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:43 +00:00
Blue Swirl
cea5f9a28f cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts.

Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h.

Compile the file without HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:38 +00:00
Peter Maydell
24e838b787 tcg/arm: Support host code being compiled for Thumb
Although the TCG generated code is always in ARM mode, it is possible
that the host code was compiled by gcc in Thumb mode (this is often the
default for Linux distributions targeting ARM v7 only). Handle this
by using BLX imm when doing a call from ARM into Thumb mode.
Since BLX imm is not a conditionalisable instruction, we make
tcg_out_call() no longer take a condition code; we were only ever
using it with COND_AL anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-24 03:27:22 +01:00
Aurelien Jarno
5677903453 tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:07 +01:00
Aurelien Jarno
0f11f25a00 tcg/arm: improve constant loading
Improve constant loading in two ways:
- On all ARM versions, it's possible to load 0xffffff00 = -0x100 using
  the mvn rd, #0. Fix the conditions.
- On <= ARMv6 versions, where movw and movt are not available, load the
  constants using mov and orr with rotations depending on the constant
  to load. This is very useful for example to load constants where the
  low byte is 0. This reduce the generated code size by about 7%.

Also fix the coding style at the same time.

Cc: Andrzej Zaborowski <balrog@zabor.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 07:30:30 +01:00
Aurelien Jarno
9a3abc21a6 tcg/arm: fix qemu_st64 for big endian targets
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of
a 64 bit word before saving it. This patch fixes that.

Acked-by: Andrzej Zaborowski <balrogg@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:41:33 +01:00
Aurelien Jarno
c69806ab82 tcg/arm: fix branch target change during code retranslation
QEMU uses code retranslation to restore the CPU state when an exception
happens. For it to work the retranslation must not modify the generated
code. This is what is currently implemented in ARM TCG.

However on CPU that don't have icache/dcache/memory synchronised like
ARM, this requirement is stronger and code retranslation must not modify
the generated code "atomically", as the cache line might be flushed
at any moment (interrupt, exception, task switching), even if not
triggered by QEMU. The probability for this to happen is very low, and
depends on cache size and associativiy, machine load, interrupts, so the
symptoms are might happen randomly.

This requirement is currently not followed in tcg/arm, for the
load/store code, which basically has the following structure:
  1) tlb access code is written
  2) conditional fast path code is written
  3) branch is written with a temporary target
  4) slow path code is written
  5) branch target is updated
The cache lines corresponding to the retranslated code is not flushed
after code retranslation as the generated code is supposed to be the
same. However if the cache line corresponding to the branch instruction
is flushed between step 3 and 5, and is not flushed again before the
code is executed again, the branch target is wrong. In the guest, the
symptoms are MMU page fault at a random addresses, which leads to
kernel page fault or segmentation faults.

The patch fixes this issue by avoiding writing the branch target until
it is known, that is by writing only the branch instruction first, and
later only the offset.

This fixes booting linux guests on ARM hosts (tested: arm, i386, mips,
mipsel, sh4, sparc).

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:39:47 +01:00
Richard Henderson
e4d58b41f9 tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:26 +02:00
Richard Henderson
3b6dac3416 tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter.  This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"
as represented by the existing TCG_TYPE_PTR.

Update all targets to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:25 +02:00
Aurelien Jarno
e23886a91d tcg/arm: fix condition in zero/sign extension functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25 05:46:22 +02:00
Aurelien Jarno
c66b5c2cb6 tcg/arm: don't try to load constants using pc
There is statistically almost 0 chances to use this code, so
remove it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
914ccf51b0 tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
bf5675efe3 tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specified
by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
2633a2d015 tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the
constraints. Don't check if they equals these registers.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
67dcab7327 tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to be
byte swapped. Two temporary registers are needed for qemu_st to do
the bswap. r0 and r1 are used in system mode, do the same in user
mode, which implies reworking the constraints.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
e854b6d39c tcg/arm: use ext* ops in qemu_ld
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
7e0d95628d tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()
functions as the ARM architecture allows that, it doesn't make sense
for qemu_ld/st functions. These functions use comparison instructions
and conditional execution already, so it is not possible to use a
second level of conditional execution.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
244b1e81f6 tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16
instructions on ARMv6+ or shifts and logical operations on previous
ARM versions. In both cases the result use less instructions than
the pure TCG version.

These ops are also needed by the qemu_ld/st functions.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
9517094f72 tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or two
shifts on previous ARM versions. In both cases the result use the same
number or less instructions than the pure TCG version.

Also move all sign extension code to separate functions, so that they
can be reused in other parts of the code.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
293579e55c tcg/arm: add rotation ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
23401b58a4 tcg/arm: use the blx instruction when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
8f7f749f21 tcg/arm: sxtb and sxth are available starting with ARMv6
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
ac34fb5c5d tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, depending
on the __ARM_ARCH_*__ GCC defines.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
2488b41bb2 tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
c8d80cef55 tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediate
values and register number. This makes the code difficult to read.

The patch below replaces all (if I haven't miss any ;-) integer values
representing register number by TCG_REG_* enum values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
f694a27ed7 tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Remove
them.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
e4a7d5e88c tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.

Also declare all the 16 registers to TCG, and mark pc as reserved.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
39221a82be tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to a
subroutine. According to the "Procedure Call Standard for the ARM
Architecture", it is the job of the callee to save this register.
Moreover, this register is already saved in the prologue/epilogue.

This patch removes the disabled SAVE_LR code, as there is no need to
reenable later.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Stefan Weil
1584c84574 tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860
did not change all occurrences of INDEX_op_qemu_ld32u
for tcg/arm.

Please note that I could not test this patch
(I have currently no arm system available).

Cc: Richard Henderson <rth@twiddle.net>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-28 16:39:52 +02:00
Richard Henderson
86feb1c860 tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand).  For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with
a given extension to a 64-bit result.  This distinction already
exists for the ld* loads, but not the qemu_ld* loads.

Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for
32-bit outputs.  Adjust all code generators to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 23:01:03 +01:00
Richard Henderson
32d98fbd10 tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:52:44 +01:00
Richard Henderson
9940a96bc8 tcg: Allow target-specific implementation of NAND.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:44:40 +01:00
Richard Henderson
8d625cf1d1 tcg: Allow target-specific implementation of EQV.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:42:46 +01:00
Richard Henderson
a975160954 tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:28:24 +01:00
Paolo Bonzini
a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 20:48:30 +01:00
Aurelien Jarno
9e97d8e941 tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the address
of the env structure and is not modified by GCC.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20 12:27:42 +01:00
Aurelien Jarno
26c5d372e4 tcg/arm: fix load/store definitions for 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20 12:10:20 +01:00
Aurelien Jarno
2b71cd72d3 tcg/arm: use helpers for divu/remu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:54 +01:00
Aurelien Jarno
31d6655100 tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers for
div/rem/divu/remu.

Create a #define for div2 so that targets can select between
div, div2 and helper implementation. Use the helper version if none
of the #define are present.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:50 +01:00
Aurelien Jarno
932234f64c tcg/arm: implement andc op
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:46:08 +01:00
Aurelien Jarno
4e17eae9f2 tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d316 QEMU crashes
on ARM hosts. This is not a bug of this commit, but a latent bug
revealed by this commit.

The TCG code is called through a procedure call using the prologue
and epilogue code. This code does not save and restore enough registers.
The "Procedure Call Standard for the ARM Architecture" says:

  A subroutine must preserve the contents of the registers r4-r8, r10,
  r11 and SP (and r9 in PCS variants that designate r9 as v6).

The current code only saves and restores r9 to r11, and misses r4 to
r8. The patch fixes that by saving r4 to r12. Theoretically there is
no need to save and restore r12, but an even number of registers have
to be saved as per EABI.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:44:25 +01:00
Paul Brook
20cb400d41 Remove TLB from userspace
Remove TLB from userspace CPU structure.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:21 +00:00
Aurelien Jarno
d3f137e355 tcg/arm: merge the two sets of #define for optional ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:12:42 +01:00
Aurelien Jarno
023e77f801 tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:31:57 +01:00
Andrzej Zaborowski
b525f0a94f Add a missing break 2010-03-02 22:26:04 +01:00
Aurelien Jarno
e0404769fa tcg/arm: implement setcond2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:19:26 +01:00
Aurelien Jarno
f72a6cd7c7 tcg/arm: implement setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:17:43 +01:00
Aurelien Jarno
6b6586131b tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skipped
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 20:19:18 +01:00
Richard Henderson
3682825669 tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:35:12 +00:00