Commit Graph

64320 Commits

Author SHA1 Message Date
Roman Bolshakov
b4e1af8961 i386: hvf: Fix register refs if REX is present
According to Intel(R)64 and IA-32 Architectures Software Developer's
Manual, the following one-byte registers should be fetched when REX
prefix is present (sorted by reg encoding index):
AL, CL, DL, BL, SPL, BPL, SIL, DIL, R8L - R15L

The first 8 are fetched if REX.R is zero, the last 8 if non-zero.

The following registers should be fetched for instructions without REX
prefix (also sorted by reg encoding index):
AL, CL, DL, BL, AH, CH, DH, BH

Current emulation code doesn't handle accesses to SPL, BPL, SIL, DIL
when REX is present, thefore an instruction 40883e "mov %dil,(%rsi)" is
decoded as "mov %bh,(%rsi)".

That caused an infinite loop in vp_reset:
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg03293.html

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Message-Id: <20181018134401.44471-1-r.bolshakov@yadro.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:12 +02:00
Vitaly Kuznetsov
6b7a98303b i386/kvm: add support for Hyper-V IPI send
Hyper-V PV IPI support is merged to KVM, enable the feature in Qemu. When
enabled, this allows Windows guests to send IPIs to other vCPUs with a
single hypercall even when there are >64 vCPUs in the request.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Roman Kagan <rkagan@virtuozzo.com>
Message-Id: <20181009130853.6412-3-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:12 +02:00
Pavel Dovgalyuk
ca9759c2a9 replay: don't process events at virtual clock checkpoint
As QEMU becomes more multi-threaded and non-synchronized, checkpoints
move from thread to thread. And the event queue that processed at checkpoints
should belong to the same thread in both record and replay executions.
This patch disables asynchronous event processing at virtual clock
checkpoint, because it may be invoked in different threads at record and
replay. This patch is temporary fix until the checkpoints are completely
refactored.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
Message-Id: <20181018063345.7433.11678.stgit@pasha-VirtualBox>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:12 +02:00
Peng Hao
a8de011500 target-i386: add q35 0xcf8 port as coalesced_pio
Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
Message-Id: <1539795177-21038-6-git-send-email-peng.hao2@zte.com.cn>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:11 +02:00
Peng Hao
37abf8d234 target-i386: add i440fx 0xcf8 port as coalesced_pio
Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
Message-Id: <1539795177-21038-5-git-send-email-peng.hao2@zte.com.cn>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:11 +02:00
Peng Hao
f98167ea06 target-i386: add rtc 0x70 port as coalesced_pio
Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
Message-Id: <1539890353-30273-1-git-send-email-peng.hao2@zte.com.cn>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:11 +02:00
Peng Hao
e6d34aeea6 target-i386 : add coalesced_pio API
the primary API realization.

Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1539795177-21038-3-git-send-email-peng.hao2@zte.com.cn>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:11 +02:00
Paolo Bonzini
966f2ec3ac linux-headers: update to 4.20-rc1
This brings in eVMCS and coalesced PIO support, as well as other features we do
not support yet.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:11 +02:00
Paolo Bonzini
b31c003895 target-i386: kvm: do not initialize padding fields
The exception.pad field is going to be renamed to pending in an upcoming
header file update.  Remove the unnecessary initialization; it was
introduced to please valgrind (commit 7e680753cf) but they were later
rendered unnecessary by commit 076796f8fd, which added the "= {}"
initializer to the declaration of "events".  Therefore the patch does
not change behavior in any way.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:04 +02:00
Artem Pisarenko
e81f86790f qemu-timer: avoid checkpoints for virtual clock timers in external subsystems
Adds EXTERNAL attribute definition to qemu timers subsystem and assigns
it to virtual clock timers, used in slirp (ICMP IPv6) and ui (key queue).
Virtual clock processing in rr mode can use this attribute instead of a
separate clock type.

Fixes: 87f4fe7653
Fixes: 775a412bf8
Fixes: 9888091404
Signed-off-by: Artem Pisarenko <artem.k.pisarenko@gmail.com>
Message-Id: <e771f96ab94e86b54b9a783c974f2af3009fe5d1.1539764043.git.artem.k.pisarenko@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:03 +02:00
Artem Pisarenko
89a603a0c8 qemu-timer: introduce timer attributes
Attributes are simple flags, associated with individual timers for their
whole lifetime.  They intended to be used to mark individual timers for
special handling when they fire.

New/init functions family in timer interface updated and refactored (new
'attribute' argument added, timer_list replaced with timer_list_group+type
combinations, comments improved to avoid info duplication).  Also existing
aio interface extended with attribute-enabled variants of functions,
which create/initialize timers.

Signed-off-by: Artem Pisarenko <artem.k.pisarenko@gmail.com>
Message-Id: <f47b81dbce734e9806f9516eba8ca588e6321c2f.1539764043.git.artem.k.pisarenko@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:03 +02:00
Artem Pisarenko
05ff8dc32f Revert some patches from recent [PATCH v6] "Fixing record/replay and adding reverse debugging"
That patch series introduced new virtual clock type for use in external
subsystems. It breaks desired behavior in non-record/replay usage
scenarios due to a small change to existing behavior.  Processing of
virtual timers belonging to new clock type is kicked off to the main
loop, which makes these timers asynchronous with vCPU thread and,
in icount mode, with whole guest execution. This breaks expected
determinism in non-record/replay icount mode of emulation where these
"external subsystems" are isolated from the host (i.e. they are
external only to guest core, not to the entire emulation environment).

Example for slirp ("user" backend for network device):
User runs qemu in icount mode with rtc clock=vm without any external
communication interfaces but with "-netdev user,restrict=on". It expects
deterministic execution, because network services are emulated inside
qemu and isolated from host. There are no reasons to get reply from DHCP
server with different delay or something like that.

The next patches revert reimplements the same changes in a better way.
This reverts commit 87f4fe7653.
This reverts commit 775a412bf8.
This reverts commit 9888091404.

Signed-off-by: Artem Pisarenko <artem.k.pisarenko@gmail.com>
Message-Id: <18b1e7c8f155fe26976f91be06bde98eef6f8751.1539764043.git.artem.k.pisarenko@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:03 +02:00
Paolo Bonzini
24f7973b67 es1370: more fixes for ADC_FRAMEADR and ADC_FRAMECNT
They are not consecutive with DAC1_FRAME* and DAC2_FRAME*; Coverity
still complains about es1370_read, while es1370_write was fixed in
commit cf9270e522.

Fixes: 154c1d1f96
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-19 13:44:00 +02:00
Peter Maydell
77f7c74719 - Updates for qtest entries in test/Makefile.include
- Simple updates for some shell scripts
 - Misc simple patches for files without regular subsystem pull requests
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABAgAGBQJbxuLDAAoJEC7Z13T+cC2144kQAJ135I3HTRLpFHEA2zj026ym
 3qW+1VmY6dSAluo/OR7ZQJfrLGCG44/Lo1OlXk07EFHcZXRImybry+dmrotDA6tK
 regbe88NLBYIx40ur388w6ZDBqsfcZspa1A0QwACxEA/BD4jZhoij4jDuxpyGXRL
 uo6UD34gU1qQPpc3JngdASK7sZsT/el2Gi6dCV5oudQg1VLbxUVRhcdqgYG/4m5H
 HpxMtdeq8nTekCRNpvDr6cjHrPBdFrBzhgXS38T+Gac/dOuJcEeiUcaH9o2ynLS4
 o74aaQfHkmO10DyKZ9rnJGsU3Hqn3zkjoxPGQR/ewUX70KR2ZVfQZiLWkWpF4gOV
 BWddr3M8DUFwTAv85qriJS5CtVn6X/DJESFEtbApMkmurhnfzXA3Ligks5beDmEn
 C82iSv/8Sl+Rt+J4zCQ4AnMaIrdKC/Ie2E65jxrbAsGynUZ0ser2Yj7CDKUWAlDZ
 l6m1p6G0TmLS6oeS6P8nMppdFhihtMD7EcglQKKLoZcbhpSD98E0jefLBh4ZqAdx
 MbFAQR9oGpOS0iLQQ/8iFe2HDRqdddw7pYNPWix74AuiGpJyVkOBPObw6QEfphe9
 6+waQ27l+x2lUYJ/ZNm6kainy0TB+SoUu8x1CQtBwv3lYU6TRrAg63ij8AXYOyPm
 bLUPeiGq3uTVzyN836Th
 =vYUc
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2018-10-17' into staging

- Updates for qtest entries in test/Makefile.include
- Simple updates for some shell scripts
- Misc simple patches for files without regular subsystem pull requests

# gpg: Signature made Wed 17 Oct 2018 08:20:35 BST
# gpg:                using RSA key 2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>"
# gpg:                 aka "Thomas Huth <thuth@redhat.com>"
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>"
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>"
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* remotes/huth-gitlab/tags/pull-request-2018-10-17:
  configure: remove glib_subprocess check
  hw/core/generic-loader: Compile only once, not for each target
  cpu: Provide a proper prototype for target_words_bigendian() in a header
  hw/core/generic-loader: Set a category for the generic-loader device
  qemu/compiler: Wrap __attribute__((flatten)) in a macro
  mailmap: Fix Reimar Döffinger name
  show-fixed-bugs.sh: Modern shell scripting (use $() instead of ``)
  git-submodule.sh: Modern shell scripting (use $() instead of ``)
  archive-source.sh: Modern shell scripting (use $() instead of ``)
  MAINTAINERS: update block/sheepdog maintainers
  gdbstub: Remove unused include
  tests: remove gcov-files- variables
  tests: Prevent more accidental test disabling
  target/cris/translate: Get rid of qemu_log_separate()
  qemu-common.h: update copyright date to 2018

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-18 13:40:19 +01:00
Peter Maydell
b151fc0e43 Queued hppa patch
-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJbxmoaAAoJEGTfOOivfiFfED8H/1d8aZJnLF4jUYsSPOc6/NyK
 ra45GAZlwC7DhMw7eppg1tI+qSNxKswcuhpHgXUOo6CV7xn7B2ajDVxpnWo4WpxC
 HTLDfMT+WmkgL1xOVEa2PYTt5ktvp0gzzZRq0ZfFnhwZzTTwYVlSaSM6eXEAhdLx
 3gUM3q0p16gHI61GKqr1QlTdDd6F814wLajyjMo/vPwnRUKy6vbvuu1JKKPM5xLg
 2H61zRX4NGCAkzARQI4qyd2o3T6G1J5NTJfwEY0HewDacXWVRVCLEb+xkGpuI2VL
 6zwifzR9pGl6lNUq0P+d4E0N8X1C0mqAkO4HyMxT6jG36nMz7dYKZkhs+VZTM2k=
 =sf5e
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20181016' into staging

Queued hppa patch

# gpg: Signature made Tue 16 Oct 2018 23:45:46 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-hppa-20181016:
  target/hppa: Raise exception 26 on emulated hardware

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-18 11:35:00 +01:00
Marc-André Lureau
7fc527cdc9 configure: remove glib_subprocess check
This should have been removed as part of commit
692fbdf9f4.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 09:01:41 +02:00
Thomas Huth
1a1ff38c55 hw/core/generic-loader: Compile only once, not for each target
The generic-loader is currently compiled target specific due to one
single "#ifdef TARGET_WORDS_BIGENDIAN" in the file. We have already a
function called target_words_bigendian() for this instead, so we can
put the generic-loader into common-obj to save some compilation time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 08:45:37 +02:00
Thomas Huth
c95ac10340 cpu: Provide a proper prototype for target_words_bigendian() in a header
We've got three places already that provide a prototype for this
function in a .c file - that's ugly. Let's provide a proper prototype
in a header instead, with a proper description why this function should
not be used in most cases.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 08:41:43 +02:00
Thomas Huth
8c827c53c5 hw/core/generic-loader: Set a category for the generic-loader device
Each device that is instantiatable by the users should be marked with
a category. Since the generic-loader does not fit anywhere else, put
it into the MISC category.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 08:40:15 +02:00
Thomas Huth
97ff87c0ed qemu/compiler: Wrap __attribute__((flatten)) in a macro
Older versions of Clang (before 3.5) and GCC (before 4.1) do not
support the "__attribute__((flatten))" yet. We don't care about
such old versions of GCC anymore, but since Clang 3.4 is still
used in EPEL for RHEL7 / CentOS 7, we should not use this attribute
directly but with a wrapper macro instead.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 08:36:28 +02:00
Philippe Mathieu-Daudé
957e8b3492 mailmap: Fix Reimar Döffinger name
This probably happened when interpreting the utf8 name as latin1.

Fixes dbbaaff686 and f4e94dfefb.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-17 08:33:53 +02:00
Helge Deller
5f538f7532 target/hppa: Raise exception 26 on emulated hardware
On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults,
while all later chips (>= PA7100) generate either trap #26, #27 or #28
(depending on the fault type).

Since the current qemu emulation emulates a B160L machine (with a
PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead
of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero.

With the patch we now get the correct output (I tested against real
hardware):
 Kernel Fault: Code=26 (Data memory access rights trap)
instead of:
 Kernel Fault: Code=18 (Data memory protection/unaligned access trap)

Signed-off-by: Helge Deller <deller@gmx.de>
Message-Id: <20181007205153.GA30270@ls3530.fritz.box>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-16 15:32:22 -07:00
Peter Maydell
09558375a6 target-arm queue:
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
  * target/arm: Fix aarch64_sve_change_el wrt EL0
  * target/arm: Define fields of ISAR registers
  * target/arm: Align cortex-r5 id_isar0
  * target/arm: Fix cortex-a7 id_isar0
  * net/cadence_gem: Fix various bugs, add support for new
    features that will be used by the Xilinx Versal board
  * target-arm: powerctl: Enable HVC when starting CPUs to EL2
  * target/arm: Add the Cortex-A72
  * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  * target/arm: Mask PMOVSR writes based on supported counters
  * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJbxhTZAAoJEDwlJe0UNgzeksAP/iHi7Oo9FMWIrGcAC2BTkwNZ
 GVGKNg2tIf4BBfuGyYpNt5s9frzQl/hRPXp323Bc6ryLwqnVsAVPhRfyLcoEoAeU
 qMA2oeCiKWacE2KbK/E2i17Mr0zynlIURVoondBzR1W2/Vdt5mRcY5+qsGhcwqUA
 Ib9SO5viWHNR/VPJjT28/kPRtBOcLkyi+/sS5q8uXBy53xxcz8iaEKMtlhMuunv8
 ar9PVuVDZ25dBkgOX5NRrxxfpV0L49sweJVWjyv7G84s/xFvbz1ZaoNrq5w5oYY/
 FmiT+kAPSEUzRHEBJwew6+QKsHWALs/0Z9ZgF6TvwJ5KFBvowMEraHbLiWcS9eCb
 h89fpftPso3TiqIZyUliDRZxIKBzRBPfRYwfuy4WxMH9O6aoJhO4UpfYwI9I2AKj
 YxuXUCtf9B6C5HRlXTdQXQSMxS04AvKs0OxM4NIO4pgazopnAaaUQuzhaZLo9VJO
 HLRZmgitOyJspxl7QeDreMK5Tb1lzLuXVSU80Tgedkx03Z2vhoIM5DcOIk5VBW8k
 KPzN0jgHHS1R2NfJ1GwaHYWtskMm3AuWQ8YDxv0bUs9f2uQQBwfiYckp5LnGd0Sz
 oAXJgb3keQBiXsCpolx665DA9NFEOF581ufup6wp4J1tBwtH0UYkFkqxPqjpWQyX
 hCUmXQQkuskpLUvRbWT9
 =T/np
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging

target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

# gpg: Signature made Tue 16 Oct 2018 17:42:01 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181016-1:
  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
  target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  target/arm: Mask PMOVSR writes based on supported counters
  target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  target/arm: Add the Cortex-A72
  target-arm: powerctl: Enable HVC when starting CPUs to EL2
  net: cadence_gem: Implement support for 64bit descriptor addresses
  net: cadence_gem: Add support for selecting the DMA MemoryRegion
  net: cadence_gem: Add support for extended descriptors
  net: cadence_gem: Add macro with max number of descriptor words
  net: cadence_gem: Use uint32_t for 32bit descriptor words
  net: cadence_gem: Disable TSU feature bit
  target/arm: Fix cortex-a7 id_isar0
  target/arm: Align cortex-r5 id_isar0
  target/arm: Define fields of ISAR registers
  target/arm: Fix aarch64_sve_change_el wrt EL0
  hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:42:56 +01:00
Mao Zhongyi
aa2192bf14 show-fixed-bugs.sh: Modern shell scripting (use $() instead of ``)
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:34:19 +02:00
Mao Zhongyi
a436cd8826 git-submodule.sh: Modern shell scripting (use $() instead of ``)
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:34:19 +02:00
Mao Zhongyi
934821ebae archive-source.sh: Modern shell scripting (use $() instead of ``)
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:34:19 +02:00
Peter Maydell
2ef297af07 coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
Add a new Coccinelle script which replaces uses of the inplace
byteswapping functions *_to_cpus() and cpu_to_*s() with their
not-in-place equivalents. This is useful for where the swapping
is done on members of a packed struct -- taking the address
of the member to pass it to an inplace function is undefined
behaviour in C.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181009181612.10633-1-peter.maydell@linaro.org
2018-10-16 17:14:55 +01:00
Peter Maydell
ab44c7b71f target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo
struct, which they fill in only if a fault occurs. This means that
the caller must always zero-initialize the struct before passing
it in. We forgot to do this in v7m_stack_read() and v7m_stack_write().
Correct the error.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011172057.9466-1-peter.maydell@linaro.org
2018-10-16 17:14:55 +01:00
Aaron Lindsay
599b71e277 target/arm: Mask PMOVSR writes based on supported counters
This is an amendment to my earlier patch:
    commit 7ece99b17e
    Author: Aaron Lindsay <alindsay@codeaurora.org>
    Date:   Thu Apr 26 11:04:39 2018 +0100

	target/arm: Mask PMU register writes based on PMCR_EL0.N

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181010203735.27918-3-aclindsa@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:14:55 +01:00
Aaron Lindsay
fc5f6856a0 target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
I previously fixed this for PMINTENSET_EL1, but missed these.

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181010203735.27918-2-aclindsa@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:14:55 +01:00
Edgar E. Iglesias
f11b452b95 target/arm: Add the Cortex-A72
Add the ARM Cortex-A72.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-11-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:14:55 +01:00
Edgar E. Iglesias
86278c33d1 target-arm: powerctl: Enable HVC when starting CPUs to EL2
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:14:55 +01:00
Edgar E. Iglesias
357aa01335 net: cadence_gem: Implement support for 64bit descriptor addresses
Implement support for 64bit descriptor addresses.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-8-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:13:50 +01:00
Edgar E. Iglesias
84aec8efd6 net: cadence_gem: Add support for selecting the DMA MemoryRegion
Add support for selecting the Memory Region that the GEM
will do DMA to.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20181011021931.4249-7-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:13:49 +01:00
Edgar E. Iglesias
e48fdd9d90 net: cadence_gem: Add support for extended descriptors
Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-6-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:13:49 +01:00
Edgar E. Iglesias
8568313f3b net: cadence_gem: Add macro with max number of descriptor words
Add macro with max number of DMA descriptor words.
No functional change.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:13:48 +01:00
Edgar E. Iglesias
f02361822f net: cadence_gem: Use uint32_t for 32bit descriptor words
Use uint32_t instead of unsigned to describe 32bit descriptor words.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-4-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 17:13:47 +01:00
Liu Yuan
53d593d25b MAINTAINERS: update block/sheepdog maintainers
E-mail to one of block/sheepdog maintainers Mitake Hitoshi bounces

<mitake.hitoshi@lab.ntt.co.jp>: unknown user: "mitake.hitoshi"

and no current address is known. So just remove it.

Signed-off-by: Liu Yuan <liuyuan1@cmiot.chinamobile.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:13:30 +02:00
Philippe Mathieu-Daudé
d417eb1d3f gdbstub: Remove unused include
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:10:55 +02:00
Paolo Bonzini
26830e9325 tests: remove gcov-files- variables
Commit 31d2dda ("build-system: remove per-test GCOV reporting", 2018-06-20)
removed users of the variables, since those uses can be replaced by a simple
overall report produced by gcovr.  However, the variables were never removed.
Do it now.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[thuth: Fixed up contextual conflicts with the patch from Eric]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:07:23 +02:00
Eric Blake
7a6c377f6b tests: Prevent more accidental test disabling
GNU make is perfectly happy to use 'check-FOO-y += bar' to
initialize check-FOO-y.  (GNU Automake strictly insists that
you cannot use += until after an initial = per variable, but
thankfully we aren't using automake).

As we have had more than one instance where copy-and-paste of
'check-FOO-y = bar' from a first test under category FOO into
an additional test, which ends up disabling the first (see
commits 992159c7 and 4429532b), it's better to just always use
the form that survives copy-and-paste, even for categories that
don't currently add more than one test.

Done with s/^\(check-[a-z]*-y \)=/\1+=/g

Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 18:02:42 +02:00
Thomas Huth
ba3fa397a1 target/cris/translate: Get rid of qemu_log_separate()
The gen_BUG() function calls already cpu_abort(), which prints the
information to stderr and the log already. So instead of additionally
printing the dc->pc via fprintf() and qemu_log here, too, we can
simply pass this information to cpu_abort() instead.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 17:57:23 +02:00
John Arbuckle
c3776f4de5 qemu-common.h: update copyright date to 2018
Currently the copyright date is set to 2017. Update the date to say
2018.

Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16 17:52:06 +02:00
Edgar E. Iglesias
b2d43091b5 net: cadence_gem: Disable TSU feature bit
Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:16:42 +01:00
Richard Henderson
37bdda89eb target/arm: Fix cortex-a7 id_isar0
The incorrect value advertised only thumb2 div without arm div.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181008212205.17752-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:16:42 +01:00
Richard Henderson
aaab8f3400 target/arm: Align cortex-r5 id_isar0
The missing nibble made it more difficult to read.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181008212205.17752-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:16:42 +01:00
Richard Henderson
a62e62af9f target/arm: Define fields of ISAR registers
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181008212205.17752-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:16:42 +01:00
Richard Henderson
9a05f7b674 target/arm: Fix aarch64_sve_change_el wrt EL0
At present we assert:

  arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed.

The comment in arm_el_is_aa64 explains why asking about EL0 without
extra information is impossible.  Add an extra argument to provide
it from the surrounding context.

Fixes: 0ab5953b00
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181008212205.17752-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:16:42 +01:00
Jerome Forissier
fb23d693a3 hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
Bindings for /secure-chosen and /secure-chosen/stdout-path have been
proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2].
They've now been officially agreed on, so we can implement them
in QEMU.

This patch creates the property when the machine is secure.

[1] https://patchwork.kernel.org/patch/9602401/
[2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Message-id: 20181005080729.6480-1-jerome.forissier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tweak]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16 16:15:01 +01:00
Peter Maydell
dddb37495b VFIO updates 2018-10-15
- ramfb support for vfio-pci via new -nohotplug device variant
    (Gerd Hoffmann)
 
  - Preparation for generic DT pass-through in vfio-platform
    (Geert Uytterhoeven & Eric Auger)
 
  - vfio-pci QOM fixups (Li Qiang)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJbxM3FAAoJECObm247sIsi2F4P/3V2hpE6YEYHpHWCLZ8ZN1Us
 WTTubHZJHBweQOTpRZxbby3oyi82f3ybGAFIkd/by8Pta0llOI7uZHJPPpGXe89c
 88Dq2IynLB6kOkbTwukxqwAChVQ9aPMc/pTWCP8FWJXWpbU+lL5JjrkNS9eo6NPZ
 /oWucQu7T6WqOJ96r/luGzOepXMcHJbrxqq7gyLHje+29S1UCu/hclhsefj6dSjx
 HQgIkn+sK4/mhfjEP5/5MmgzJS2yhxNvtGr7/Qr8m4BThkrjCpEF9SvLYg4E0EDO
 6DhjuXEPr81IrCT/ZDPk9rj1rxM7+CiYh9Udfu6vyaj67U2nJNdmShRXnDbQiNEB
 /pGseF+wYR4WAmd+66vkdpw6AdABDjgx/ReyGZjyDXpTM7ct4WtMcwm2mTFGKyc0
 /+OVCro/RmiySgrvUI7uGCL9MvBwPmtyK8kPKt+e2GKnhxJCcH4n8GiK3JiDw9qF
 w8XMTMzHUsOcQdwpsGoo0ojKjA6yxt82/i0zfV81k/7943y7NySyXa3HEsNe1qhN
 OXOI8tnWVDsxwnVNytqVxPa5iiob1nTiTXa0TiV9Pk1ZnBMpdM3SZCIWfcd9tgry
 1J+sxql+pkVU9p1oBV/oUCnmjrNlMJr4Xj6rcG8S10BDREMna+VXZtmc9SJwwJ2Y
 WQf417NklqVFjBGnxKNZ
 =j/tw
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging

VFIO updates 2018-10-15

 - ramfb support for vfio-pci via new -nohotplug device variant
   (Gerd Hoffmann)

 - Preparation for generic DT pass-through in vfio-platform
   (Geert Uytterhoeven & Eric Auger)

 - vfio-pci QOM fixups (Li Qiang)

# gpg: Signature made Mon 15 Oct 2018 18:26:29 BST
# gpg:                using RSA key 239B9B6E3BB08B22
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>"
# gpg:                 aka "Alex Williamson <alex@shazbot.org>"
# gpg:                 aka "Alex Williamson <alwillia@redhat.com>"
# gpg:                 aka "Alex Williamson <alex.l.williamson@gmail.com>"
# Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B  8A90 239B 9B6E 3BB0 8B22

* remotes/awilliam/tags/vfio-updates-20181015.0:
  vfio-pci: make vfio-pci device more QOM conventional
  hw/arm/virt: Allow dynamic vfio-platform devices again
  hw/arm/sysbus-fdt: Allow device matching with DT compatible value
  vfio/platform: Make the vfio-platform device non-abstract
  hw/vfio/display: add ramfb support
  stubs: add ramfb

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-15 18:44:04 +01:00