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4 Commits

Author SHA1 Message Date
Richard Henderson
e4ea952fb0 hw/misc: Constify VMState 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>
 2023-12-30 07:38:06 +11:00
Francisco Iglesias
975dd496b5 hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR 
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-5-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2023-09-08 16:41:35 +01:00
Francisco Iglesias
ebfdc49428 hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO 
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-4-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2023-09-08 16:41:35 +01:00
Francisco Iglesias
86d916c621 hw/misc: Introduce a model of Xilinx Versal's CFU_APB 
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-3-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2023-09-08 16:41:34 +01:00