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hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR

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Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-5-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Francisco Iglesias 2023-08-31 17:56:57 +01:00 committed by Peter Maydell
parent ebfdc49428
commit 975dd496b5
2 changed files with 102 additions and 0 deletions
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87
hw/misc/xlnx-versal-cfu.c
View File

@ -264,6 +264,31 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
}
}
static uint64_t cfu_sfr_read(void *opaque, hwaddr addr, unsigned size)
{
qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
HWADDR_PRIx "\n", __func__, addr);
return 0;
}
static void cfu_sfr_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(opaque);
uint32_t wfifo[WFIFO_SZ];
if (update_wfifo(addr, value, s->wfifo, wfifo)) {
uint8_t row_addr = extract32(wfifo[0], 23, 5);
uint32_t frame_addr = extract32(wfifo[0], 0, 23);
XlnxCfiPacket pkt = { .reg_addr = CFRAME_SFR,
.data[0] = frame_addr };
if (s->cfg.cfu) {
cfu_transfer_cfi_packet(s->cfg.cfu, row_addr, &pkt);
}
}
}
static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
{
XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
@ -293,6 +318,16 @@ static const MemoryRegionOps cfu_stream_ops = {
},
};
static const MemoryRegionOps cfu_sfr_ops = {
.read = cfu_sfr_read,
.write = cfu_sfr_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static const MemoryRegionOps cfu_fdro_ops = {
.read = cfu_fdro_read,
.write = cfu_fdro_write,
@ -334,6 +369,23 @@ static void cfu_apb_init(Object *obj)
sysbus_init_irq(sbd, &s->irq_cfu_imr);
}
static void cfu_sfr_init(Object *obj)
{
XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem_sfr, obj, &cfu_sfr_ops, s,
TYPE_XLNX_VERSAL_CFU_SFR, KEYHOLE_STREAM_4K);
sysbus_init_mmio(sbd, &s->iomem_sfr);
}
static void cfu_sfr_reset_enter(Object *obj, ResetType type)
{
XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(obj);
memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t));
}
static void cfu_fdro_init(Object *obj)
{
XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
@ -401,6 +453,12 @@ static Property cfu_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
static Property cfu_sfr_props[] = {
DEFINE_PROP_LINK("cfu", XlnxVersalCFUSFR, cfg.cfu,
TYPE_XLNX_VERSAL_CFU_APB, XlnxVersalCFUAPB *),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_cfu_apb = {
.name = TYPE_XLNX_VERSAL_CFU_APB,
.version_id = 1,
@ -423,6 +481,16 @@ static const VMStateDescription vmstate_cfu_fdro = {
}
};
static const VMStateDescription vmstate_cfu_sfr = {
.name = TYPE_XLNX_VERSAL_CFU_SFR,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFUSFR, 4),
VMSTATE_END_OF_LIST(),
}
};
static void cfu_apb_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -443,6 +511,16 @@ static void cfu_fdro_class_init(ObjectClass *klass, void *data)
rc->phases.enter = cfu_fdro_reset_enter;
}
static void cfu_sfr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
device_class_set_props(dc, cfu_sfr_props);
dc->vmsd = &vmstate_cfu_sfr;
rc->phases.enter = cfu_sfr_reset_enter;
}
static const TypeInfo cfu_apb_info = {
.name = TYPE_XLNX_VERSAL_CFU_APB,
.parent = TYPE_SYS_BUS_DEVICE,
@ -467,10 +545,19 @@ static const TypeInfo cfu_fdro_info = {
}
};
static const TypeInfo cfu_sfr_info = {
.name = TYPE_XLNX_VERSAL_CFU_SFR,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XlnxVersalCFUSFR),
.class_init = cfu_sfr_class_init,
.instance_init = cfu_sfr_init,
};
static void cfu_apb_register_types(void)
{
type_register_static(&cfu_apb_info);
type_register_static(&cfu_fdro_info);
type_register_static(&cfu_sfr_info);
}
type_init(cfu_apb_register_types)

15
include/hw/misc/xlnx-versal-cfu.h
View File

@ -28,6 +28,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
#define TYPE_XLNX_VERSAL_CFU_SFR "xlnx,versal-cfu-sfr"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUSFR, XLNX_VERSAL_CFU_SFR)
REG32(CFU_ISR, 0x0)
FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
@ -222,6 +225,18 @@ struct XlnxVersalCFUFDRO {
Fifo32 fdro_data;
};
struct XlnxVersalCFUSFR {
SysBusDevice parent_obj;
MemoryRegion iomem_sfr;
/* 128-bit wfifo. */
uint32_t wfifo[WFIFO_SZ];
struct {
XlnxVersalCFUAPB *cfu;
} cfg;
};
/**
* This is a helper function for updating a CFI data write fifo, an array of 4
* uint32_t and 128 bits of data that are allowed to be written through 4