The core file contains register's value. These APIs write registers to
core file, and them will be called in the following patch.
Signed-off-by: Wen Congyang <wency@cn.fujitsu.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Walk cpu's page table and collect all virtual address and physical address mapping.
Then, add these mapping into memory mapping list. If the guest does not use paging,
it will do nothing. Note: the I/O memory will be skipped.
Signed-off-by: Wen Congyang <wency@cn.fujitsu.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
The memory mapping list stores virtual address and physical address mapping.
The virtual address and physical address are contiguous in the mapping.
The folloing patch will use this information to create PT_LOAD in the vmcore.
Signed-off-by: Wen Congyang <wency@cn.fujitsu.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
* 'cocoa-for-upstream' of git://repo.or.cz/qemu/afaerber:
Drop darwin-user
configure: add '--disable-cocoa' switch
raw-posix: Do not use CONFIG_COCOA macro
* 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu:
Makefile: Simplify compilation of target-*/cpu.c
target-mips: Start QOM'ifying CPU init
target-mips: QOM'ify CPU
target-m68k: Add QOM CPU subclasses
target-m68k: Start QOM'ifying CPU init
target-m68k: QOM'ify CPU reset
target-m68k: QOM'ify CPU
target-sh4: Start QOM'ifying CPU init
target-sh4: QOM'ify CPU reset
target-sh4: QOM'ify CPU
MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes
MAINTAINERS: Downgrade target-m68k to Odd Fixes
It's been orphaned, not compiling for a long time and despite Apple's
drop of their Rosetta ppc emulation technology with Mac OS X Lion no one
has stepped up to fix it.
Testing necessary changes wrt QOM'ification thus is impossible, so we
might as well remove it completely.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Embed CPUMIPSState as first member of QOM MIPSCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Embed CPUM68KState as first member of QOM M68kCPU.
Drop cpu_m68k_close() in favor of object_delete().
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Laurent Vivier <Laurent@Vivier.EU>
Tested-by: Laurent Vivier <Laurent@Vivier.EU>
Embed CPUSH4State as first member of SuperHCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Autoconf concept of "datadir" is supposed to be "$prefix/share", not
"$prefix/share/PACKAGE", so using datadir for the Qemu-specific
directory is confusing.
The current C code that uses CONFIG_QEMU_DATADIR should be safe, as now
create_config generates the same #define name (CONFIG_QEMU_DATADIR) for
both "datadir" and "qemu_datadir" variables.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Embed CPUMBState as first member of QOM MicroBlazeCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Tested-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
[AF: Updated cpu.c to include cpu-qom.h indirectly via cpu.h]
Embed CPUCRISState as first member of QOM CRISCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
* origin/master: (27 commits)
target-arm: Move reset handling to arm_cpu_reset
target-arm: Drop cpu_reset_model_id()
target-arm: Move cache ID register setup to cpu specific init fns
target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
target-arm: Move feature register setup to per-CPU init fns
target-arm: Move iWMMXT wCID reset to cpu_state_reset
target-arm: Drop JTAG_ID documentation
target-arm: Move SCTLR reset value setup to per cpu init fns
target-arm: Move CTR setup to per cpu init fns
target-arm: Move MVFR* setup to per cpu init fns
target-arm: Move FPSID config to cpu init fns
target-arm: Move feature bit settings to CPU init fns
target-arm: Add QOM subclasses for each ARM cpu implementation
target-arm: remind to keep arm features in sync with linux-user/elfload.c
tci: GETPC() macro must return an uintptr_t
gdbstub: Synchronize CPU state unconditionally in gdb_set_cpu_pc
softfloat: make USE_SOFTFLOAT_STRUCT_TYPES compile
target-xtensa: add tests for LOOPNEZ and LOOPGTZ
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
qtest: add m48t59 tests for Sparc
...
The versatile i2c controller implementation was separated to
its own file called versatile_i2c.c. This is done as a preparation
for adding i2c support to the versatilepb board.
Signed-off-by: Oskar Andero <oskar.andero@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The tracetool script is written in shell and has hit several portability
problems due to shell quirks or external tools across host platforms.
Additionally the amount of string processing and lack of real data
structures makes it tough to implement code generator backends for
tracers that are more complex.
This patch replaces the shell version of tracetool with a Python
version. The new tracetool design is:
scripts/tracetool.py - top-level script
scripts/tracetool/backend/ - tracer backends live here (simple, ust)
scripts/tracetool/format/ - output formats live here (.c, .h)
There is common code for trace-events definition parsing so that
backends can focus on generating code rather than parsing input.
Support for all existing backends (nop, stderr, simple, ust,
and dtrace) is added back in follow-up patches.
[Commit description written by Stefan Hajnoczi]
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* sstabellini/for_anthony:
xen: introduce an event channel for buffered io event notifications
xen-mapcache: don't unmap locked entry during mapcache invalidation
Xen, mapcache: Fix the compute of the size of bucket.
xen: handle backend deletion from xenstore
Xen: Add xen-apic support and hook it up.
Xen: basic HVM MSI injection support.
This is Diamond 233L Standard Core Rev.C (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa:
target-xtensa: Start QOM'ifying CPU init
target-xtensa: QOM'ify CPU reset
target-xtensa: QOM'ify CPU
target-xtensa: improve unit tests debugging
target-xtensa: Move helpers.h to helper.h
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
hw/arm_gic: Remove stray hardcoded tab
hw/arm_gic: gic_set_pending_private() is NVIC only
hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define
hw/arm_gic: Make gic_reset a sysbus reset function
hw/arm11mpcore: Convert to using sysbus GIC device
hw/exynos4210_gic: Convert to using sysbus GIC
hw/realview_gic: switch to sysbus GIC
hw/a9mpcore: Switch to using sysbus GIC
hw/a15mpcore: switch to using sysbus GIC
hw/arm_gic: Make the GIC its own sysbus device
hw/arm_gic: Expose PPI inputs as gpio inputs
hw/arm_gic: Move gic_get_current_cpu into arm_gic.c
hw/arm_gic: Move NCPU definition to arm_gic.c
hw/exynos4210_combiner.c: Drop excessive read/write access check.
ARM: Exynos4210: Drop gic_cpu_write() after initialization.
Fix bit test in Exynos4210 UART emulation to use & instead of &&
Embed CPUXtensaState as first member of XtensaCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Compile arm_gic.c as a standalone C file to produce a self contained
sysbus GIC device. Support the legacy usage by #include of the .c file
by making those users #define LEGACY_INCLUDED_GIC, so we can convert
them one by one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
Embed CPULM32State as first member of QOM LM32CPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michael Walle <michael@walle.cc>
Align QOM'ified targets, with a view to simplify Makefile.target.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Embed CPUS390XState as first member of S390CPU.
Since -cpu is being ignored, make TYPE_S390_CPU non-abstract.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Tested-by: Christian Borntraeger <borntraeger@de.ibm.com>
* stefanha/tracing:
tracetool: dtrace: handle in and next reserved words
tracetool: dtrace disabled-events fix
Makefile.target: code stp dependency on trace-events
* 'qom-cpu-unicore32.v3' of git://github.com/afaerber/qemu-cpu:
target-unicore32: Move CPU-dependent init into initfn
target-unicore32: QOM'ify CPU
target-unicore32: License future contributions under GPLv2+
target-unicore32: Relicense to GPLv2+
MAINTAINERS: Add entry for UniCore32
Embed CPUUniCore32State as first member of UniCore32CPU.
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Introduce only one non-abstract type TYPE_ARM_CPU and do not touch
cp15 registers to not interfere with Peter's ongoing remodelling.
Embed CPUARMState as first (additional) field of ARMCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This completes the transition away from AREG0. This patch must
be last because it requires CONFIG_TCG_PASS_AREG0 set too.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Adjust generation of load and store templates so that the functions
take a parameter for CPUState instead of relying on global env.
Remove wrappers. Move remaining memory helpers to ldst_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kraxel/usb.44:
Endian fix an assertion in usb-msd
uhci: alloc can't fail, drop check.
uhci: new uhci_handle_td return code for tds still in flight
uhci: renumber uhci_handle_td return codes
uhci: use enum for uhci_handle_td return codes
uhci: tracing support
uhci: cancel on schedule stop.
uhci: fix uhci_async_cancel_all
uhci: pass addr to uhci_async_alloc
usb: improve packet state sanity checks
usb-ohci: DMA writeback bug fixes
usb-ehci: drop unused isoch_pause variable
usb: zap hw/ush-{ohic,uhci}.h + init wrappers
usb: the big rename
Link the Object base class and the module infrastructure for class
registration. Introduce $(universal-obj-y) for objects that are more
common than $(common-obj-y), so that those only get built once.
Call QOM module init for type registration.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Reorganize usb source files. Create a new hw/usb/ directory and move
all usb source code to that place. Also make filenames a bit more
descriptive. Host adapters are prefixed with "hch-" now, usb device
emulations are prefixed with "dev-". Fixup paths Makefile and include
paths to make it compile. No code changes.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This provides the required user space stubs to enable the in-kernel
i8254 emulation of KVM.
The in-kernel model supports lost tick compensation according to the
"delay" policy. This is enabled by default and can be switched off via a
device property.
Depending on the feature set of the host kernel (before 2.6.32), we may
have to disable the HPET or lack sound output from the PC speaker.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Device model for cadence gem ethernet controller.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Implemented cadence UART serial controller
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
